From 709ee1b8423bb45f2131f05af469bc6c7a18649a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 4 Jan 2021 17:17:35 -0700 Subject: [PATCH] [HDL] Update dff netlist for SCFF used in configuration chain --- openfpga_flow/openfpga_cell_library/verilog/dff.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index 9838a6b6a..a0548c54c 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -414,12 +414,12 @@ module CFGSDFFR ( input SI, // Scan-chain input input CFGE, // Configure enable output Q, // Regular Q output - output QN, // Regular Qb output output CFGQ, // Data Q output which is released when configure enable is activated output CFGQN // Data Qb output which is released when configure enable is activated ); //------------Internal Variables-------- reg q_reg; +wire QN; //-------------Code Starts Here--------- always @ ( posedge CK or posedge RST) @@ -432,7 +432,7 @@ end else begin end assign CFGQ = CFGE ? Q : 1'b0; -assign CFGQN = CFGE ? QN : 1'b0; +assign CFGQN = CFGE ? QN : 1'b1; `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q