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fixed a bug in using tileable routing when directlist is enabled

This commit is contained in:
tangxifan 2020-03-20 16:38:58 -06:00
parent c5049a1ec8
commit 708fda9606
12 changed files with 70 additions and 7 deletions
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2
libs/libarchfpga/src/read_xml_arch_file.cpp
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@ -2536,7 +2536,7 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti
//Expect only tileable attributes on <layout>
//expect_only_attributes(layout_tag, {"tileable"}, loc_data);
arch->tileable = get_attribute(layout_tag, "tileable", loc_data).as_bool();
arch->tileable = get_attribute(layout_tag, "tileable", loc_data).as_bool(false);
//Count the number of <auto_layout> or <fixed_layout> tags
size_t auto_layout_cnt = 0;

2
openfpga/test_script/and_k6_frac_adder_chain.openfpga
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@ -1,5 +1,5 @@
# Run VPR for the 'and' design
vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
# Read OpenFPGA architecture definition
read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml

6
openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
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@ -160,13 +160,15 @@
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout tileable="true">
<auto_layout aspect_ratio="1.0">
<!--auto_layout aspect_ratio="1.0"-->
<fixed_layout name="2x2" width="3" height="4">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</auto_layout>
</fixed_layout>
<!-- /auto_layout -->
</layout>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM

3
vpr/src/base/SetupVPR.cpp
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@ -321,6 +321,9 @@ static void SetupRoutingArch(const t_arch& Arch,
/* copy over the switch block information */
RoutingArch->switchblocks = Arch.switchblocks;
/* Copy the tileable routing setting */
RoutingArch->tileable = Arch.tileable;
}
static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) {

5
vpr/src/base/place_and_route.cpp
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@ -88,6 +88,11 @@ int binary_search_place_and_route(const t_placer_opts& placer_opts_ref,
graph_type = GRAPH_GLOBAL;
} else {
graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR);
/* Branch on tileable routing */
if ( (UNI_DIRECTIONAL == det_routing_arch->directionality)
&& (true == det_routing_arch->tileable) ) {
graph_type = GRAPH_UNIDIR_TILEABLE;
}
}
best_routing = alloc_saved_routing();

2
vpr/src/base/vpr_api.cpp
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@ -831,7 +831,7 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi
graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR);
/* Branch on tileable routing */
if ( (UNI_DIRECTIONAL == det_routing_arch->directionality)
&& (true == arch.tileable) ) {
&& (true == det_routing_arch->tileable) ) {
graph_type = GRAPH_UNIDIR_TILEABLE;
}
}

3
vpr/src/base/vpr_types.h
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@ -1010,6 +1010,9 @@ struct t_det_routing_arch {
int subFs;
enum e_switch_block_type switch_block_subtype;
/* Xifan Tang: tileable routing */
bool tileable;
short global_route_switch;
short delayless_switch;
int wire_to_arch_ipin_switch;

5
vpr/src/route/route_common.cpp
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@ -269,6 +269,11 @@ bool try_route(int width_fac,
graph_type = GRAPH_GLOBAL;
} else {
graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR);
/* Branch on tileable routing */
if ( (UNI_DIRECTIONAL == det_routing_arch->directionality)
&& (true == det_routing_arch->tileable) ) {
graph_type = GRAPH_UNIDIR_TILEABLE;
}
}
/* Set the channel widths */

14
vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
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@ -59,6 +59,20 @@ e_side determine_io_grid_pin_side(const vtr::Point<size_t>& device_size,
}
}
/* Deteremine the side of a pin of a grid */
std::vector<e_side> find_grid_pin_sides(const t_grid_tile& grid,
const size_t& pin_id) {
std::vector<e_side> pin_sides;
for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT} ) {
if (true == grid.type->pinloc[grid.width_offset][grid.height_offset][size_t(side)][pin_id]) {
pin_sides.push_back(side);
}
}
return pin_sides;
}
/************************************************************************
* Get a list of pin_index for a grid (either OPIN or IPIN)
* For IO_TYPE, only one side will be used, we consider one side of pins

3
vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
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@ -20,6 +20,9 @@ size_t find_unidir_routing_channel_width(const size_t& chan_width);
int get_grid_pin_class_index(const t_grid_tile& cur_grid,
const int pin_index);
std::vector<e_side> find_grid_pin_sides(const t_grid_tile& grid,
const size_t& pin_id);
e_side determine_io_grid_pin_side(const vtr::Point<size_t>& device_size,
const vtr::Point<size_t>& grid_coordinate);

8
vpr/src/tileable_rr_graph/rr_gsb.cpp
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@ -822,6 +822,14 @@ void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph,
get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index);
/* Must have valid side and index */
if (NUM_SIDES == side) {
VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y());
VTR_LOG("SRC node:\n");
rr_graph.print_node(src_node);
VTR_LOG("Channel node:\n");
rr_graph.print_node(chan_node);
}
VTR_ASSERT(NUM_SIDES != side);
VTR_ASSERT(OPEN != index);

24
vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
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@ -1391,12 +1391,32 @@ void build_direct_connections_for_one_gsb(RRGraph& rr_graph,
int from_grid_height_ofs = from_grid.height_offset;
int to_grid_width_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].width_offset;
int to_grid_height_ofs = grids[to_grid_coordinate.x()][to_grid_coordinate.y()].height_offset;
/* Find the side of grid pins, the pin location should be unique!
* Pin location is required by searching a node in rr_graph
*/
std::vector<e_side> opin_grid_side = find_grid_pin_sides(from_grid, opin);
VTR_ASSERT(1 == opin_grid_side.size());
std::vector<e_side> ipin_grid_side = find_grid_pin_sides(grids[to_grid_coordinate.x()][to_grid_coordinate.y()], ipin);
VTR_ASSERT(1 == ipin_grid_side.size());
const RRNodeId& opin_node_id = rr_graph.find_node(from_grid_coordinate.x() - from_grid_width_ofs,
from_grid_coordinate.y() - from_grid_height_ofs,
OPIN, opin);
OPIN, opin, opin_grid_side[0]);
const RRNodeId& ipin_node_id = rr_graph.find_node(to_grid_coordinate.x() - to_grid_width_ofs,
to_grid_coordinate.y() - to_grid_height_ofs,
IPIN, ipin);
IPIN, ipin, ipin_grid_side[0]);
/*
VTR_LOG("Direct connection: from grid[%lu][%lu].pin[%lu] at side %s to grid[%lu][%lu].pin[%lu] at side %s\n",
from_grid_coordinate.x() - from_grid_width_ofs,
from_grid_coordinate.y() - from_grid_height_ofs,
opin, SIDE_STRING[opin_grid_side[0]],
to_grid_coordinate.x() - to_grid_width_ofs,
to_grid_coordinate.y() - to_grid_height_ofs,
ipin, SIDE_STRING[ipin_grid_side[0]]);
*/
/* add edges to the opin_node */
rr_graph.create_edge(opin_node_id, ipin_node_id,
delayless_switch);