diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml
index 1f4108593..2b695027a 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml
@@ -146,7 +146,7 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch_set_reset_set_reset" prefix="config_latch_set_reset_set_reset" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch_set_reset_set_reset.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch_set_reset_set_reset.v">
+    <circuit_model type="sram" name="config_latch_set_reset" prefix="config_latch_set_reset" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch_set_reset.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch_set_reset.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>