From 7028e4e3b8839e72224beb2ec3b52015d16472ad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Dec 2022 14:22:19 -0800 Subject: [PATCH] [doc] rename cicid rst file. Fixed a few bugs on image sizes and broken format --- .../{ci_cd_setup/index.rst => cicd_setup.rst} | 11 +++++++---- docs/source/dev_manual/index.rst | 8 ++++---- docs/source/dev_manual/version_number.rst | 2 ++ docs/source/overview/motivation.rst | 10 +++++----- 4 files changed, 18 insertions(+), 13 deletions(-) rename docs/source/dev_manual/{ci_cd_setup/index.rst => cicd_setup.rst} (97%) diff --git a/docs/source/dev_manual/ci_cd_setup/index.rst b/docs/source/dev_manual/cicd_setup.rst similarity index 97% rename from docs/source/dev_manual/ci_cd_setup/index.rst rename to docs/source/dev_manual/cicd_setup.rst index 8d4802d82..773e07efb 100644 --- a/docs/source/dev_manual/ci_cd_setup/index.rst +++ b/docs/source/dev_manual/cicd_setup.rst @@ -1,6 +1,7 @@ +.. dev_manual_cicd_setup:: CI/CD setup ------------- +----------- OpenFPGA implements CI/CD system using Github actions. The following figure shows the Actions implements flow. @@ -70,13 +71,15 @@ in which case the docker image compiled for the latest master branch is used for The OpenFPGA soure is compiled with the following set of compilers. - #. gcc-5 - #. gcc-6 #. gcc-7 #. gcc-8 #. gcc-9 - #. clang-6.0 + #. gcc-10 + #. gcc-11 + #. clang-6 + #. clang-7 #. clang-8 + #. clang-10 The docker images for these build enviroment are available on `github packages `_. diff --git a/docs/source/dev_manual/index.rst b/docs/source/dev_manual/index.rst index 6640ab320..23b744f50 100644 --- a/docs/source/dev_manual/index.rst +++ b/docs/source/dev_manual/index.rst @@ -2,10 +2,10 @@ .. toctree:: :maxdepth: 1 - ci_cd_setup/index - version_number - regression_tests - back_compatible + + cicd_setup + + regression_tests diff --git a/docs/source/dev_manual/version_number.rst b/docs/source/dev_manual/version_number.rst index 612f15721..feabce41f 100644 --- a/docs/source/dev_manual/version_number.rst +++ b/docs/source/dev_manual/version_number.rst @@ -33,11 +33,13 @@ To update the version number, please follow the rules: Version updates are made in the following scenario - When a minor milestone is achieved, the minor revision number can be increased by 1. The following condition is considered as a minor milestone: + - a new feature has been developed. - a critical patch has been applied. - a sufficient number of small patches has been applied in the past quarter. In other words, the minor revision will be updated by the end of each quarter as long as there are patches. - When several minor milestones are achieved, the major revision number can be increased by 1. The following condition is considered as a major milestone: + - significant improvements on Quality-of-Results (QoR). - significant changes on user interface. - a techical feature is developed and validated by the community, which can impact the complete design flow. diff --git a/docs/source/overview/motivation.rst b/docs/source/overview/motivation.rst index a7315ef52..58693d7fe 100644 --- a/docs/source/overview/motivation.rst +++ b/docs/source/overview/motivation.rst @@ -12,7 +12,7 @@ OpenFPGA aims to be an open-source framework that enables rapid prototyping of c .. _fig_openfpga_motivation: .. figure:: ./figures/openfpga_motivation.png - :scale: 50% + :width: 100% :alt: OpenFPGA: a fast prototyping framework for customizable FPGAs Comparison on engineering time and effort to prototype an FPGA using OpenFPGA and conventional approaches [All the layout figures are publishable under the proper licenses] @@ -28,7 +28,7 @@ The rest of this section will focus on detailed motivation for each of them, as .. _fig_openfpga_framework: .. figure:: ./figures/openfpga_framework.svg - :scale: 50% + :width: 100% :alt: OpenFPGA framework OpenFPGA: a unified framework for chip designer and FPGA programmer @@ -49,7 +49,7 @@ programmable fabric and the configuration peripheral. .. _fig_openfpga_arch_lang_coverage: .. figure:: ./figures/openfpga_arch_lang_coverage.png - :scale: 15% + :width: 100% :alt: OpenFPGA architecture description language enabling fully customizable FPGA architecture and circuit-level implementation OpenFPGA architecture description language enabling fully customizable FPGA architecture and circuit-level implementation @@ -68,7 +68,7 @@ FPGA-Verilog is designed to output flexible and standard Verilog netlists, enabl .. _fig_fpga_verilog_motivation: .. figure:: ./figures/fpga_verilog_motivation.svg - :scale: 25% + :width: 100% :alt: Flexible netlist format support by FPGA-Verilog to enable various backend choices FPGA-Verilog enabling flexible backend flows @@ -88,7 +88,7 @@ Our flow automatically generates two sets of SDC files. .. _fig_fpga_sdc_motivation: .. figure:: ./figures/fpga_sdc_motivation.png - :scale: 25% + :width: 100% :alt: FPGA-SDC enabling iterative timing constrained backend flow FPGA-SDC enabling iterative timing constrained backend flow