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[Doc] An example to the documentation about the new feature in tile_annotation

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tangxifan 2022-03-20 13:12:13 +08:00
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docs/source/manual/arch_lang/annotate_vpr_arch.rst
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@ -134,6 +134,16 @@ When a global port, e.g., ``clk``, is defined in ``tile_annotation`` using the f
</global_port> </global_port>
</tile_annotations> </tile_annotations>
Note that a global port can also be defined to drive only a partial bit of a port of a physical tile.
.. code-block:: xml
<tile_annotations>
<global_port name="clk" is_clock="true">
<tile name="clb" port="clk[3:3]"/>
</global_port>
</tile_annotations>
Clock port ``clk`` of each ``clb`` tile will be connected to a common clock port of the top module, while local clock network is customizable through VPR's architecture description language. For instance, the local clock network can be a programmable clock network. Clock port ``clk`` of each ``clb`` tile will be connected to a common clock port of the top module, while local clock network is customizable through VPR's architecture description language. For instance, the local clock network can be a programmable clock network.
.. _annotate_vpr_arch_pb_type_annotation: .. _annotate_vpr_arch_pb_type_annotation: