[Tool] Add tile annotation parser
This commit is contained in:
tangxifan
parent
d127304760
commit
6fbdbe68ae
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@ -9,6 +9,7 @@
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#include "simulation_setting.h"
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#include "config_protocol.h"
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#include "arch_direct.h"
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#include "tile_annotation.h"
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#include "pb_type_annotation.h"
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/* namespace openfpga begins */
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@ -51,6 +52,11 @@ struct Arch {
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*/
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ArchDirect arch_direct;
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/* Physical tile annotations:
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* Global port definition for tile ports
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*/
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TileAnnotation tile_annotations;
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/* Pb type annotations
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* Bind from operating to physical
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* Bind from physical to circuit model
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@ -21,6 +21,7 @@
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#include "read_xml_simulation_setting.h"
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#include "read_xml_config_protocol.h"
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#include "read_xml_routing_circuit.h"
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#include "read_xml_tile_annotation.h"
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#include "read_xml_pb_type_annotation.h"
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#include "read_xml_openfpga_arch.h"
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#include "openfpga_arch_linker.h"
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@ -103,6 +104,9 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
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openfpga_arch.arch_direct = read_xml_direct_circuit(xml_openfpga_arch, loc_data,
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openfpga_arch.circuit_lib);
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/* Parse the pb_type annotation */
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openfpga_arch.tile_annotations = read_xml_tile_annotations(xml_openfpga_arch, loc_data);
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/* Parse the pb_type annotation */
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openfpga_arch.pb_type_annotations = read_xml_pb_type_annotations(xml_openfpga_arch, loc_data);
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@ -0,0 +1,93 @@
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/********************************************************************
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* This file includes the top-level function of this library
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* which reads an XML modeling OpenFPGA architecture to the associated
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* data structures
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*******************************************************************/
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#include <string>
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/* Headers from pugi XML library */
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#include "pugixml.hpp"
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#include "pugixml_util.hpp"
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/* Headers from vtr util library */
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#include "vtr_assert.h"
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/* Headers from libarchfpga */
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#include "arch_error.h"
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#include "read_xml_util.h"
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/* Headers from libopenfpgautil */
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#include "openfpga_tokenizer.h"
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#include "openfpga_port_parser.h"
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#include "read_xml_tile_annotation.h"
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/********************************************************************
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* Parse XML description for an interconnection annotation
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* under a <global_port> XML node
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*******************************************************************/
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static
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void read_xml_tile_global_port_annotation(pugi::xml_node& xml_tile,
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const pugiutil::loc_data& loc_data,
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openfpga::TileAnnotation& tile_annotation) {
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/* We have two mandatory XML attributes
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* 1. name of the port
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* 2. name of the tile and ports in the format of <tile_name>.<tile_port_name>
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*/
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const std::string& name_attr = get_attribute(xml_tile, "name", loc_data).as_string();
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const std::string& tile_port_name_attr = get_attribute(xml_tile, "tile_port", loc_data).as_string();
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/* Extract the tile name */
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openfpga::StringToken tokenizer(tile_port_name_attr);
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std::vector<std::string> tile_port_tokens = tokenizer.split('.');
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if (2 != tile_port_tokens.size()) {
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archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tile),
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"Invalid tile_port attribute '%s'! Valid format is <tile_name>.<port_name>\n",
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tile_port_name_attr);
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}
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/* Extract the tile port information */
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openfpga::PortParser tile_port_parser(tile_port_tokens[1]);
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TileGlobalPortId tile_global_port_id = tile_annotation.create_global_port(name_attr, tile_port_tokens[0], tile_port_parser.port());
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/* Get is_clock attributes */
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tile_annotation.set_global_port_is_clock(tile_global_port_id, get_attribute(xml_tile, "is_clock", loc_data).as_bool(false));
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/* Get is_set attributes */
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tile_annotation.set_global_port_is_set(tile_global_port_id, get_attribute(xml_tile, "is_set", loc_data).as_bool(false));
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/* Get is_reset attributes */
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tile_annotation.set_global_port_is_reset(tile_global_port_id, get_attribute(xml_tile, "is_reset", loc_data).as_bool(false));
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/* Get default_value attributes */
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tile_annotation.set_global_port_default_value(tile_global_port_id, get_attribute(xml_tile, "default_value", loc_data).as_int(0));
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}
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/********************************************************************
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* Top function to parse XML description about tile annotation
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*******************************************************************/
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openfpga::TileAnnotation read_xml_tile_annotations(pugi::xml_node& Node,
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const pugiutil::loc_data& loc_data) {
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openfpga::TileAnnotation tile_annotations;
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/* Parse configuration protocol root node */
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pugi::xml_node xml_annotations = get_single_child(Node, "tile_annotations", loc_data, pugiutil::ReqOpt::OPTIONAL);
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/* Not found, we can return */
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if (!xml_annotations) {
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return tile_annotations;
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}
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/* Iterate over the children under this node,
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* each child should be named after <pb_type>
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*/
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for (pugi::xml_node xml_tile_global_port : xml_annotations.children()) {
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/* Error out if the XML child has an invalid name! */
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if (xml_tile_global_port.name() != std::string("global_port")) {
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bad_tag(xml_tile_global_port, loc_data, xml_annotations, {"global_port"});
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}
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read_xml_tile_global_port_annotation(xml_tile_global_port, loc_data, tile_annotations);
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}
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return tile_annotations;
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}
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@ -0,0 +1,17 @@
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#ifndef READ_XML_TILE_ANNOTATION_H
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#define READ_XML_TILE_ANNOTATION_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "pugixml_util.hpp"
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#include "pugixml.hpp"
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#include "tile_annotation.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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openfpga::TileAnnotation read_xml_tile_annotations(pugi::xml_node& Node,
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const pugiutil::loc_data& loc_data);
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#endif
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@ -0,0 +1,115 @@
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/************************************************************************
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* Member functions for class TileAnnotation
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***********************************************************************/
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#include "vtr_assert.h"
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#include "tile_annotation.h"
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/* namespace openfpga begins */
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namespace openfpga {
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/************************************************************************
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* Constructors
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***********************************************************************/
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TileAnnotation::TileAnnotation() {
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return;
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}
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/************************************************************************
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* Public Accessors : aggregates
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***********************************************************************/
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TileAnnotation::global_port_range TileAnnotation::global_ports() const {
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return vtr::make_range(global_port_ids_.begin(), global_port_ids_.end());
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}
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/************************************************************************
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* Public Accessors
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***********************************************************************/
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std::string TileAnnotation::global_port_name(const TileGlobalPortId& global_port_id) const {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_names_[global_port_id];
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}
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std::string TileAnnotation::global_port_tile_name(const TileGlobalPortId& global_port_id) const {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_tile_names_[global_port_id];
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}
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BasicPort TileAnnotation::global_port_tile_port(const TileGlobalPortId& global_port_id) const {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_tile_ports_[global_port_id];
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}
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bool TileAnnotation::global_port_is_clock(const TileGlobalPortId& global_port_id) const {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_is_clock_[global_port_id];
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}
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bool TileAnnotation::global_port_is_set(const TileGlobalPortId& global_port_id) const {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_is_set_[global_port_id];
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}
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bool TileAnnotation::global_port_is_reset(const TileGlobalPortId& global_port_id) const {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_is_reset_[global_port_id];
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}
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size_t TileAnnotation::global_port_default_value(const TileGlobalPortId& global_port_id) const {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_default_values_[global_port_id];
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}
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/************************************************************************
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* Public Mutators
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***********************************************************************/
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TileGlobalPortId TileAnnotation::create_global_port(const std::string& port_name,
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const std::string& tile_name,
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const BasicPort& tile_port) {
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/* This is a legal name. we can create a new id */
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TileGlobalPortId port_id = TileGlobalPortId(global_port_ids_.size());
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global_port_ids_.push_back(port_id);
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global_port_names_.push_back(port_name);
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global_port_tile_names_.push_back(tile_name);
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global_port_tile_ports_.push_back(tile_port);
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global_port_is_clock_.push_back(false);
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global_port_is_set_.push_back(false);
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global_port_is_reset_.push_back(false);
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global_port_default_values_.push_back(0);
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return port_id;
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}
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void TileAnnotation::set_global_port_is_clock(const TileGlobalPortId& global_port_id,
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const bool& is_clock) {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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global_port_is_clock_[global_port_id] = is_clock;
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}
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void TileAnnotation::set_global_port_is_set(const TileGlobalPortId& global_port_id,
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const bool& is_set) {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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global_port_is_set_[global_port_id] = is_set;
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}
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void TileAnnotation::set_global_port_is_reset(const TileGlobalPortId& global_port_id,
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const bool& is_reset) {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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global_port_is_reset_[global_port_id] = is_reset;
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}
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void TileAnnotation::set_global_port_default_value(const TileGlobalPortId& global_port_id,
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const size_t& default_value) {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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global_port_default_values_[global_port_id] = default_value;
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}
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/************************************************************************
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* Internal invalidators/validators
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***********************************************************************/
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/* Validators */
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bool TileAnnotation::valid_global_port_id(const TileGlobalPortId& global_port_id) const {
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return ( size_t(global_port_id) < global_port_ids_.size() ) && ( global_port_id == global_port_ids_[global_port_id] );
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}
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} /* namespace openfpga ends */
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@ -0,0 +1,80 @@
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#ifndef TILE_ANNOTATION_H
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#define TILE_ANNOTATION_H
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/********************************************************************
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* Include header files required by the data structure definition
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*******************************************************************/
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#include <vector>
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#include <map>
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#include <array>
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#include "vtr_vector.h"
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#include "openfpga_port.h"
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#include "tile_annotation_fwd.h"
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/* namespace openfpga begins */
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namespace openfpga {
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/********************************************************************
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* This file include the declaration of data structures
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* to store physical tile annotation, including
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* 1. global port definition where a tile port can be treated as a
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* global port of the FPGA fabric
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*
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* Note:
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* 1. Keep this data structure as general as possible. It is supposed
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* to contain the raw data from architecture XML! If you want to link
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* to other data structures, please create another one in other header files
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*******************************************************************/
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class TileAnnotation {
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public: /* Types */
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typedef vtr::vector<TileGlobalPortId, TileGlobalPortId>::const_iterator global_port_iterator;
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/* Create range */
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typedef vtr::Range<global_port_iterator> global_port_range;
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public: /* Constructor */
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TileAnnotation();
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public: /* Public accessors: aggregators */
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global_port_range global_ports() const;
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public: /* Public accessors */
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std::string global_port_name(const TileGlobalPortId& global_port_id) const;
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std::string global_port_tile_name(const TileGlobalPortId& global_port_id) const;
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BasicPort global_port_tile_port(const TileGlobalPortId& global_port_id) const;
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bool global_port_is_clock(const TileGlobalPortId& global_port_id) const;
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bool global_port_is_set(const TileGlobalPortId& global_port_id) const;
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bool global_port_is_reset(const TileGlobalPortId& global_port_id) const;
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size_t global_port_default_value(const TileGlobalPortId& global_port_id) const;
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public: /* Public mutators */
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/* By default, we do not set it as a clock.
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* Users should set it through the set_global_port_is_clock() function
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*/
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TileGlobalPortId create_global_port(const std::string& port_name,
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const std::string& tile_name,
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const BasicPort& tile_port);
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void set_global_port_is_clock(const TileGlobalPortId& global_port_id,
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const bool& is_clock);
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void set_global_port_is_set(const TileGlobalPortId& global_port_id,
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const bool& is_set);
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void set_global_port_is_reset(const TileGlobalPortId& global_port_id,
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const bool& is_reset);
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void set_global_port_default_value(const TileGlobalPortId& global_port_id,
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const size_t& default_value);
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public: /* Public validator */
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bool valid_global_port_id(const TileGlobalPortId& global_port_id) const;
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private: /* Internal data */
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/* Global port information for tiles */
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vtr::vector<TileGlobalPortId, TileGlobalPortId> global_port_ids_;
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vtr::vector<TileGlobalPortId, std::string> global_port_names_;
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vtr::vector<TileGlobalPortId, std::string> global_port_tile_names_;
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vtr::vector<TileGlobalPortId, BasicPort> global_port_tile_ports_;
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vtr::vector<TileGlobalPortId, bool> global_port_is_clock_;
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vtr::vector<TileGlobalPortId, bool> global_port_is_reset_;
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vtr::vector<TileGlobalPortId, bool> global_port_is_set_;
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vtr::vector<TileGlobalPortId, size_t> global_port_default_values_;
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};
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} /* namespace openfpga ends */
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#endif
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@ -0,0 +1,22 @@
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/************************************************************************
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* A header file for TileAnnotation class, including critical data declaration
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* Please include this file only for using any TileAnnotation data structure
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* Refer to tile_annotation.h for more details
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***********************************************************************/
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/************************************************************************
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* Create strong id for tile global ports to avoid illegal type casting
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***********************************************************************/
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#ifndef TILE_ANNOTATION_FWD_H
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#define TILE_ANNOTATION_FWD_H
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#include "vtr_strong_id.h"
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struct tile_global_port_id_tag;
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typedef vtr::StrongId<tile_global_port_id_tag> TileGlobalPortId;
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/* Short declaration of class */
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class TileAnnotation;
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#endif
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