diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp index b978b200d..315f647bc 100644 --- a/openfpga/src/base/openfpga_bitstream.cpp +++ b/openfpga/src/base/openfpga_bitstream.cpp @@ -76,6 +76,7 @@ int build_fabric_bitstream(OpenfpgaContext& openfpga_ctx, /* Build fabric bitstream here */ openfpga_ctx.mutable_fabric_bitstream() = build_fabric_dependent_bitstream(openfpga_ctx.bitstream_manager(), openfpga_ctx.module_graph(), + openfpga_ctx.arch().circuit_lib, openfpga_ctx.arch().config_protocol, cmd_context.option_enable(cmd, opt_verbose)); diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp index 9065a6ae5..216f44354 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp @@ -490,6 +490,7 @@ void rec_build_module_fabric_dependent_frame_bitstream(const BitstreamManager& b *******************************************************************/ static void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, const ModuleManager& module_manager, @@ -577,7 +578,7 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc break; } case CONFIG_MEM_QL_MEMORY_BANK: { - build_module_fabric_dependent_bitstream_ql_memory_bank(config_protocol, + build_module_fabric_dependent_bitstream_ql_memory_bank(config_protocol, circuit_lib, bitstream_manager, top_block, module_manager, top_module, fabric_bitstream); @@ -702,6 +703,7 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc *******************************************************************/ FabricBitstream build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager, const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, const bool& verbose) { FabricBitstream fabric_bitstream; @@ -720,7 +722,7 @@ FabricBitstream build_fabric_dependent_bitstream(const BitstreamManager& bitstre VTR_ASSERT(0 == top_module_name.compare(bitstream_manager.block_name(top_block[0]))); /* Start build-up formally */ - build_module_fabric_dependent_bitstream(config_protocol, + build_module_fabric_dependent_bitstream(config_protocol, circuit_lib, bitstream_manager, top_block[0], module_manager, top_module, fabric_bitstream); diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.h b/openfpga/src/fpga_bitstream/build_fabric_bitstream.h index 3daadde75..8905b03a5 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.h +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.h @@ -6,6 +6,7 @@ *******************************************************************/ #include #include "config_protocol.h" +#include "circuit_library.h" #include "bitstream_manager.h" #include "fabric_bitstream.h" #include "module_manager.h" @@ -19,6 +20,7 @@ namespace openfpga { FabricBitstream build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager, const ModuleManager& module_manager, + const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, const bool& verbose); diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp index 1fefa79b2..5399832b2 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp @@ -19,6 +19,7 @@ #include "decoder_library_utils.h" #include "bitstream_manager_utils.h" +#include "memory_bank_utils.h" #include "build_fabric_bitstream_memory_bank.h" /* begin namespace openfpga */ @@ -48,8 +49,11 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B const ConfigRegionId& config_region, const size_t& bl_addr_size, const size_t& wl_addr_size, - const size_t& num_bls, - const size_t& num_wls, + const std::map& num_bls_per_tile, + const std::map& bl_start_index_per_tile, + const std::map& num_wls_per_tile, + const std::map& wl_start_index_per_tile, + vtr::Point& tile_coord, size_t& cur_mem_index, FabricBitstream& fabric_bitstream, const FabricBitRegionId& fabric_bitstream_region) { @@ -79,6 +83,10 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B ModuleId child_module = configurable_children[child_id]; size_t child_instance = module_manager.region_configurable_child_instances(parent_module, config_region)[child_id]; + if (parent_module == top_module) { + tile_coord = module_manager.region_configurable_child_coordinates(parent_module, config_region)[child_id]; + } + /* Get the instance name and ensure it is not empty */ std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance); @@ -87,12 +95,19 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B /* We must have one valid block id! */ VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block)); + /* Reset the memory index for each children under the top-level module */ + if (parent_module == top_module) { + cur_mem_index = 0; + } + /* Go recursively */ rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(bitstream_manager, child_block, module_manager, top_module, child_module, config_region, bl_addr_size, wl_addr_size, - num_bls, num_wls, + num_bls_per_tile, bl_start_index_per_tile, + num_wls_per_tile, wl_start_index_per_tile, + tile_coord, cur_mem_index, fabric_bitstream, fabric_bitstream_region); @@ -131,7 +146,9 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B module_manager, top_module, child_module, config_region, bl_addr_size, wl_addr_size, - num_bls, num_wls, + num_bls_per_tile, bl_start_index_per_tile, + num_wls_per_tile, wl_start_index_per_tile, + tile_coord, cur_mem_index, fabric_bitstream, fabric_bitstream_region); @@ -151,11 +168,11 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B FabricBitId fabric_bit = fabric_bitstream.add_bit(config_bit); /* Find BL address */ - size_t cur_bl_index = std::floor(cur_mem_index / num_bls); + size_t cur_bl_index = bl_start_index_per_tile.at(tile_coord.x()) + std::floor(cur_mem_index / num_bls_per_tile.at(tile_coord.x())); std::vector bl_addr_bits_vec = itobin_charvec(cur_bl_index, bl_addr_size); /* Find WL address */ - size_t cur_wl_index = cur_mem_index % num_wls; + size_t cur_wl_index = wl_start_index_per_tile.at(tile_coord.y()) + cur_mem_index % num_wls_per_tile.at(tile_coord.y()); std::vector wl_addr_bits_vec = itobin_charvec(cur_wl_index, wl_addr_size); /* Set BL address */ @@ -180,6 +197,7 @@ void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(const B * by considering the configuration protocol types *******************************************************************/ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, const ModuleManager& module_manager, @@ -221,13 +239,33 @@ void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol /* Build the bitstream for all the blocks in this region */ FabricBitRegionId fabric_bitstream_region = fabric_bitstream.add_region(); + + /************************************************************** + * Precompute the BLs and WLs distribution across the FPGA fabric + * The distribution is a matrix which contains the starting index of BL/WL for each column or row + */ + std::pair child_x_range = compute_memory_bank_regional_configurable_child_x_range(module_manager, top_module, config_region); + std::pair child_y_range = compute_memory_bank_regional_configurable_child_y_range(module_manager, top_module, config_region); + + std::map num_bls_per_tile = compute_memory_bank_regional_bitline_numbers_per_tile(module_manager, top_module, + config_region, + circuit_lib, config_protocol.memory_model()); + std::map num_wls_per_tile = compute_memory_bank_regional_wordline_numbers_per_tile(module_manager, top_module, + config_region, + circuit_lib, config_protocol.memory_model()); + + std::map bl_start_index_per_tile = compute_memory_bank_regional_blwl_start_index_per_tile(child_x_range, num_bls_per_tile); + std::map wl_start_index_per_tile = compute_memory_bank_regional_blwl_start_index_per_tile(child_y_range, num_wls_per_tile); + + vtr::Point temp_coord; rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(bitstream_manager, top_block, module_manager, top_module, top_module, config_region, bl_addr_port_info.get_width(), wl_addr_port_info.get_width(), - bl_port_info.get_width(), - wl_port_info.get_width(), + num_bls_per_tile, bl_start_index_per_tile, + num_wls_per_tile, wl_start_index_per_tile, + temp_coord, cur_mem_index, fabric_bitstream, fabric_bitstream_region); diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.h b/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.h index 41174a2fe..58d511394 100644 --- a/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.h +++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.h @@ -6,6 +6,7 @@ *******************************************************************/ #include #include "config_protocol.h" +#include "circuit_library.h" #include "bitstream_manager.h" #include "fabric_bitstream.h" #include "module_manager.h" @@ -18,6 +19,7 @@ namespace openfpga { void build_module_fabric_dependent_bitstream_ql_memory_bank(const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, const ModuleManager& module_manager,