diff --git a/libopenfpga/libpcf/src/pin_constraints.cpp b/libopenfpga/libpcf/src/pin_constraints.cpp
index e48d8bf57..24d7571b7 100644
--- a/libopenfpga/libpcf/src/pin_constraints.cpp
+++ b/libopenfpga/libpcf/src/pin_constraints.cpp
@@ -39,7 +39,7 @@ std::string PinConstraints::net(const PinConstraintId& pin_constraint_id) const
 }
 
 std::string PinConstraints::pin_net(const openfpga::BasicPort& pin) const {
-  std::string constrained_net_name = std::string(PIN_CONSTRAINT_OPEN_NET);
+  std::string constrained_net_name;
   for (const PinConstraintId& pin_constraint : pin_constraints()) {
     if (pin == pin_constraint_pins_[pin_constraint]) {
       constrained_net_name = net(pin_constraint); 
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index a5647638a..25b1abe5f 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -137,15 +137,16 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
         /* If the clock port name is in the pin constraints, we should wire it to the constrained pin */
         std::string constrained_net_name = pin_constraints.pin_net(module_clock_pin);
 
-        /* If there is no clock in the benchmark, we assign it to a default value */
-        if (true == benchmark_clock_port_names.empty()) {
+        /* If constrained to an open net or there is no clock in the benchmark, we assign it to a default value */
+        if ( (std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name)
+          || (true == benchmark_clock_port_names.empty())) {
           std::vector<size_t> default_values(1, fabric_global_ports.global_port_default_value(global_port_id));
           print_verilog_wire_constant_values(fp, module_clock_pin, default_values);
           continue;
         }
 
         std::string clock_name_to_connect;
-        if (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name) {
+        if (!constrained_net_name.empty()) {
           clock_name_to_connect = constrained_net_name;
         } else {
           /* Otherwise, we must have a clear one-to-one clock net corresponding!!! */
@@ -177,7 +178,8 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
       /* - If constrained to a given net in the benchmark, we connect the global pin to the net
        * - If constrained to an open net in the benchmark, we assign it to a default value 
        */
-      if (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name) {
+      if ( (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name)
+        && (!constrained_net_name.empty())) {
         BasicPort benchmark_pin(constrained_net_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 1);
         print_verilog_wire_connection(fp, module_global_pin, benchmark_pin, false);
       } else {
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 11f3777f2..7a233de1a 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -409,7 +409,8 @@ void print_verilog_top_testbench_global_reset_ports_stimuli(std::fstream& fp,
         std::string constrained_net_name = pin_constraints.pin_net(module_global_pin);
 
         /* - If constrained to a given net in the benchmark, we connect the global pin to the net */
-        if (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name) {
+        if ( (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name)
+          && (!constrained_net_name.empty())) {
           BasicPort benchmark_pin(constrained_net_name, 1);
           print_verilog_wire_connection(fp, module_global_pin,
                                         benchmark_pin,