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[Tool] Patch the critical bug in the use of signal polarity in pin constraints

This commit is contained in:
tangxifan 2021-07-02 15:26:21 -06:00
parent 3aacce2a96
commit 6e6c3e9fa4
4 changed files with 17 additions and 8 deletions
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7
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -105,6 +105,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
const std::string& reference_verilog_top_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
@ -125,6 +126,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
prefix_to_remove,
std::string(BENCHMARK_PORT_POSTFIX),
atom_ctx, netlist_annotation,
pin_constraints,
explicit_port_mapping);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@ -213,10 +215,6 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp,
if (1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)))) {
initial_value = 0;
}
/* Pin constraints has the final decision on the default value */
if (pin_constraints.valid_net_default_value(block_name)) {
initial_value = pin_constraints.net_default_value_to_int(block_name);
}
fp << "initial" << std::endl;
fp << "\tbegin" << std::endl;
@ -308,6 +306,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
if (!options.no_self_checking()) {
print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name,
atom_ctx, netlist_annotation,
pin_constraints,
options.explicit_port_mapping());
}

10
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -69,6 +69,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& output_port_postfix,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
const bool& use_explicit_port_map) {
/* Validate the file stream */
valid_file_stream(fp);
@ -99,6 +100,15 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
if (true == use_explicit_port_map) {
fp << "." << block_name << module_input_port_postfix << "(";
}
/* Polarity of some input may have to be inverted, as defined in pin constraints
* For example, the reset signal of the benchmark is active low
* while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted)
* However, to ensure correct stimuli to the benchmark, we have to invert the signal
*/
if (LOGIC_HIGH == pin_constraints.net_default_value(block_name)) {
fp << "~";
}
fp << block_name;
if (true == use_explicit_port_map) {
fp << ")";

1
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -38,6 +38,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& output_port_postfix,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
const bool& use_explicit_port_map);
void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,

7
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -912,6 +912,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
const std::string& reference_verilog_top_name,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const PinConstraints& pin_constraints,
const bool& explicit_port_mapping) {
/* Validate the file stream */
valid_file_stream(fp);
@ -932,6 +933,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
prefix_to_remove,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
atom_ctx, netlist_annotation,
pin_constraints,
explicit_port_mapping);
print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------"));
@ -1789,11 +1791,7 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp,
continue;
}
/* Pin constraints has the final decision on the default value */
size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)));
if (pin_constraints.valid_net_default_value(block_name)) {
initial_value = pin_constraints.net_default_value_to_int(block_name);
}
/* Connect stimuli to greset with an optional inversion, depending on the default value */
BasicPort reset_port(block_name, 1);
@ -2004,6 +2002,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
circuit_name,
atom_ctx,
netlist_annotation,
pin_constraints,
explicit_port_mapping);
}