riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

start to support direct mapping to MUX2 standard cells

This commit is contained in:
tangxifan 2019-07-17 07:54:23 -06:00
parent d6dfc29508
commit 6e1d49d74e
6 changed files with 120 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml
View File

@ -269,6 +269,7 @@
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="on" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="on" circuit_model_name="buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="6"/>

3
vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h
View File

@ -55,7 +55,8 @@ enum e_spice_model_pass_gate_logic_type {
enum e_spice_model_gate_type {
SPICE_MODEL_GATE_AND,
SPICE_MODEL_GATE_OR
SPICE_MODEL_GATE_OR,
SPICE_MODEL_GATE_MUX2
};
/* Transistor-level basic informations*/

4
vpr7_x2p/libarchfpga/SRC/read_xml_spice.c
View File

@ -616,8 +616,10 @@ static void ProcessSpiceModelGate(ezxml_t Node,
gate_info->type = SPICE_MODEL_GATE_AND;
} else if (0 == strcmp(FindProperty(Node,"topology",TRUE),"OR")) {
gate_info->type = SPICE_MODEL_GATE_OR;
} else if (0 == strcmp(FindProperty(Node,"topology",TRUE),"MUX2")) {
gate_info->type = SPICE_MODEL_GATE_MUX2;
} else {
vpr_printf(TIO_MESSAGE_ERROR,"[LINE %d] Invalid topology of gates. Should be [AND|OR].\n",
vpr_printf(TIO_MESSAGE_ERROR,"[LINE %d] Invalid topology of gates. Should be [AND|OR|MUX2].\n",
Node->line);
exit(1);
}

68
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -1104,6 +1104,19 @@ void dump_verilog_mux_basis_module(FILE* fp,
spice_mux_model->spice_mux_arch,
spice_mux_model->size);
/* Exception: if tgate is a standard cell, we skip the basis circuit generation */
t_spice_model* tgate_spice_model = spice_mux_model->spice_model->pass_gate_logic->spice_model;
if (SPICE_MODEL_GATE == tgate_spice_model->type) {
assert (SPICE_MODEL_GATE_MUX2 == tgate_spice_model->design_tech_info.gate_info->type);
/* Double check the mux structure, which should be tree-like */
if ( SPICE_MODEL_STRUCTURE_TREE != spice_mux_model->spice_mux_arch->structure ) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of Circuit model (%s) should be tree-like because it is linked to a 2:1 MUX!\n",
__FILE__, __LINE__, spice_mux_model->spice_model->name);
exit(1);
}
return;
}
/* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */
/*
if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) {
@ -1228,6 +1241,60 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
out_idx = j/2;
/* Each basis mux2to1: <given_name> <input0> <input1> <output> <sram> <sram_inv> svdd sgnd <subckt_name> */
fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */
/* For MUX2 standard cell */
t_spice_model* tgate_spice_model = spice_model.pass_gate_logic->spice_model;
/* For non-standard cells */
if (SPICE_MODEL_GATE == tgate_spice_model->type) {
assert(SPICE_MODEL_GATE_MUX2 == tgate_spice_model->design_tech_info.gate_info->type);
int num_input_port = 0;
int num_output_port = 0;
t_spice_model_port** input_port = NULL;
t_spice_model_port** output_port = NULL;
/* Quick check on the number of ports */
assert(3 == num_input_port); /* A, B and SEL */
assert(1 == num_output_port); /* OUT */
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(", input_port[0]->lib_name);
}
/* For intermediate buffers */
if (TRUE == inter_buf_loc[level]) {
fprintf(fp, "mux2_l%d_in_buf[%d]", level, j); /* input0 */
} else {
fprintf(fp, "mux2_l%d_in[%d]", level, j); /* input0 */
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(", input_port[1]->lib_name);
}
/* For intermediate buffers */
if (TRUE == inter_buf_loc[level]) {
fprintf(fp, "mux2_l%d_in_buf[%d]", level, nextj); /* input1 */
} else {
fprintf(fp, "mux2_l%d_in[%d]", level, nextj); /* input1 */
}
if (true == is_explicit_mapping) {
fprintf(fp, "), .%s(", output_port[0]->lib_name);
} else {
fprintf(fp, ", ");
}
fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
if (true == is_explicit_mapping) {
fprintf(fp, "), .%s(", input_port[2]->lib_name);
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */
if (true == is_explicit_mapping) {
fprintf(fp, "));\n");
} else {
fprintf(fp, ");\n");
}
} else {
assert (SPICE_MODEL_PASSGATE == tgate_spice_model->type);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
@ -1264,6 +1331,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
} else {
fprintf(fp, ");\n");
}
}
/* For intermediate buffers */
if (TRUE == inter_buf_loc[nextlevel]) {
/* Find the input port, output port, and sram port*/

7
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -2921,10 +2921,17 @@ char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,
int mux_size, char* postfix) {
char* mux_subckt_name = NULL;
/* If the tgate spice model of this MUX is a MUX2 standard cell,
* the mux_subckt name will be the name of the standard cell
*/
if ( SPICE_MODEL_GATE_MUX2 == spice_model->pass_gate_logic->spice_model->type) {
mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name);
} else {
mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5
+ strlen(my_itoa(mux_size)) + strlen(postfix) + 1));
sprintf(mux_subckt_name, "%s_size%d%s",
spice_model->name, mux_size, postfix);
}
return mux_subckt_name;
}

2
vpr7_x2p/vpr/regression_verilog.sh
View File

@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
cd -
# Run VPR
#echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping"
echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping"
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping
cd $fpga_flow_scripts