From 6e1b58f8a66353c5aba4d2945088711d12cc5022 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 17 Apr 2021 15:05:22 -0600 Subject: [PATCH] [Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports --- .../verilog_preconfig_top_module.cpp | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 542eadc2e..d55a59834 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -173,8 +173,32 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp, } /* For other ports, give an default value */ - std::vector default_values(module_global_port.get_width(), fabric_global_ports.global_port_default_value(global_port_id)); - print_verilog_wire_constant_values(fp, module_global_port, default_values); + for (size_t pin_id = 0; pin_id < module_global_port.pins().size(); ++pin_id) { + BasicPort module_global_pin(module_global_port.get_name(), + module_global_port.pins()[pin_id], + module_global_port.pins()[pin_id]); + + /* If the global port name is in the pin constraints, we should wire it to the constrained pin */ + std::string constrained_net_name = std::string(PIN_CONSTRAINT_OPEN_NET); + for (const PinConstraintId& pin_constraint : pin_constraints.pin_constraints()) { + if (module_global_pin == pin_constraints.pin(pin_constraint)) { + constrained_net_name = pin_constraints.net(pin_constraint); + break; + } + } + + /* - If constrained to a given net in the benchmark, we connect the global pin to the net + * - If constrained to an open net in the benchmark, we assign it to a default value + */ + if (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name) { + BasicPort benchmark_pin(constrained_net_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX), 1); + print_verilog_wire_connection(fp, module_global_pin, benchmark_pin, false); + } else { + VTR_ASSERT_SAFE(std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name); + std::vector default_values(module_global_pin.get_width(), fabric_global_ports.global_port_default_value(global_port_id)); + print_verilog_wire_constant_values(fp, module_global_pin, default_values); + } + } } print_verilog_comment(fp, std::string("----- End Connect Global ports of FPGA top module -----"));