From 6dd8d347e140d9aad6c8c72c02786240fc291166 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 May 2020 14:39:04 -0600 Subject: [PATCH] try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif --- openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf index e093b2b53..b42e17287 100644 --- a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf @@ -22,11 +22,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_ti [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +# Cannot pass automatically. Need change in .v file to match ports +# When passed, we can replace the and2 benchmark +#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.blif [SYNTHESIS_PARAM] bench0_top = and2 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +#bench0_top = test_mode_low +#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.act +#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/test_mode_low/test_mode_low.v bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]