diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml
index b0f8d5333..d2df1756d 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml
@@ -17,10 +17,10 @@
   <clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]"> 
     <spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
       <intermediate_driver x="1" y="1">
-        <internal_driver from_pin="clb.O[0:7]" to_pin="op_reset[0:0]"/>
+        <tap from_pin="clb.O[0:7]" to_pin="op_reset[0:0]"/>
       </intermediate_driver>
-      <switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"> 
-      <switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"> 
+      <switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"/> 
+      <switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"/> 
       <switch_point tap="rst_rib_lvl1_sw1_upper" x="2" y="1"/> 
       <switch_point tap="rst_rib_lvl1_sw1_lower" x="2" y="1"/> 
     </spine>