diff --git a/docs/source/fpga_bitstream/fabric_dependent_bitstream.rst b/docs/source/fpga_bitstream/fabric_dependent_bitstream.rst
new file mode 100644
index 000000000..280768c1a
--- /dev/null
+++ b/docs/source/fpga_bitstream/fabric_dependent_bitstream.rst
@@ -0,0 +1,7 @@
+Fabric-dependent Bitstream
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Fabric-dependent bitstream is design to be loadable to the configuration protocols of FPGAs. 
+The bitstream just sets an order to the configuration bits in the database, without duplicating the database.
+OpenFPGA framework provides a fabric-dependent bitstream generator which is aligned to our Verilog netlists.
+The fabric-dependent bitstream can be found in autogenerated Verilog testbenches.
diff --git a/docs/source/fpga_bitstream/file_organization.rst b/docs/source/fpga_bitstream/generic_bitstream.rst
similarity index 53%
rename from docs/source/fpga_bitstream/file_organization.rst
rename to docs/source/fpga_bitstream/generic_bitstream.rst
index 91975fcc7..78fbd3de4 100644
--- a/docs/source/fpga_bitstream/file_organization.rst
+++ b/docs/source/fpga_bitstream/generic_bitstream.rst
@@ -1,9 +1,21 @@
-Bitstream Output File Format
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Generic Bitstream
+~~~~~~~~~~~~~~~~~
 
-FPGA-Bitstream can generate two types of bitstreams:
+Usage
+`````
 
-* Generic bitstreams, where configuration bits are organized out-of-order in a database. We output the generic bitstream to a XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes two sets of information: 
+Generic bitstream is a fabric-independent bitstream where configuration bits are organized out-of-order in a database.
+This can be regarded as a raw bitstream used for 
+  - ``debugging``: Hardware engineers can validate if their configuration memories across the FPGA fabric are assigned to expected values 
+  - ``an exchangeable file format for bitstream assembler``: Software engineers can use the raw bitstream to build a bitstream assembler which organize the bitstream in the loadable formate to FPGA chips.
+  - ``creation of artificial bitstream``: Test engineers can craft artificial bitstreams to test each element of the FPGA fabric, which is typically not synthesizable by VPR. 
+
+.. note:: The fabric-independent bitstream cannot be directly loaded to FPGA fabrics
+
+File Format
+```````````
+
+OpenFPGA can output the generic bitstream to an XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes two sets of information: 
 
   - ``hierarchy`` represents the location of this block in FPGA fabric.
 
@@ -37,5 +49,3 @@ FPGA-Bitstream can generate two types of bitstreams:
           <bit memory_port="mem_out[15]" value="0"/>
       </bitstream>
   </bitstream_block>
-
-* Fabric-dependent bitstreams, where configuration bits are organized to be loadable to the configuration protocols of FPGAs. The bitstream just sets an order to the configuration bits in the database, without duplicating the database. OpenFPGA framework provides a fabric-dependent bitstream generator which is aligned to our Verilog netlists. The fabric-dependent bitstream can be found in autogenerated Verilog testbenches.
diff --git a/docs/source/fpga_bitstream/index.rst b/docs/source/fpga_bitstream/index.rst
index 6e1123899..e30f89354 100644
--- a/docs/source/fpga_bitstream/index.rst
+++ b/docs/source/fpga_bitstream/index.rst
@@ -1,11 +1,14 @@
 FPGA-Bitstream
 --------------
+
+FPGA-Bitstream can generate two types of bitstreams:
+
 .. _fpga_bitstream:
    FPGA-Bitstream
  
 .. toctree::
    :maxdepth: 2
   
-   file_organization
- 
-   
+   generic_bitstream
+
+   fabric_dependent_bitstream