From 6cb51d1e7d2fdd5446ea43668bc83aa8ce10ec45 Mon Sep 17 00:00:00 2001
From: Andrew Pond <apond308@gmail.com>
Date: Wed, 21 Jul 2021 14:12:32 -0600
Subject: [PATCH] timing files renamed

---
 .../misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys   | 102 +++
 ...ain_dpram1K_dsp18_fracff_skywater130nm.yml |  62 ++
 ...der_chain_dpram1K_fracff_skywater130nm.yml |  47 ++
 ...adder_chain_dsp18_fracff_skywater130nm.yml |  44 ++
 .../skywater130nm.yml                         |   8 +-
 ...ac_N4_tileable_adder_chain_mem1K_130nm.xml | 702 ++++++++++++++++++
 ...ain_dpram1K_dsp18_fracff_skywater130nm.xml |  24 +-
 7 files changed, 973 insertions(+), 16 deletions(-)
 create mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys
 create mode 100644 openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml
 create mode 100644 openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml
 create mode 100644 openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml
 create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml

diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys
new file mode 100644
index 000000000..cd7ff02b5
--- /dev/null
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys
@@ -0,0 +1,102 @@
+# Yosys synthesis script for ${TOP_MODULE}
+
+#########################
+# Parse input files
+#########################
+# Read verilog files
+${READ_VERILOG_FILE}
+# Read technology library
+read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
+
+#########################
+# Prepare for synthesis
+#########################
+# Identify top module from hierarchy
+hierarchy -check -top ${TOP_MODULE}
+# - Convert process blocks to AST
+proc
+# Flatten all the gates/primitives
+flatten
+# Identify tri-state buffers from 'z' signal in AST
+# with follow-up optimizations to clean up AST
+tribuf -logic
+opt_expr
+opt_clean
+# demote inout ports to input or output port
+# with follow-up optimizations to clean up AST
+deminout
+opt
+
+opt_expr
+opt_clean
+check
+opt
+wreduce -keepdc
+peepopt
+pmuxtree
+opt_clean
+
+########################
+# Map multipliers
+# Inspired from synth_xilinx.cc
+#########################
+# Avoid merging any registers into DSP, reserve memory port registers first
+memory_dff
+
+#########################
+# Run coarse synthesis
+#########################
+# Run a tech map with default library
+techmap
+alumacc
+share
+opt
+fsm
+# Run a quick follow-up optimization to sweep out unused nets/signals
+opt -fast
+# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells  
+memory -nomap
+opt_clean
+
+#########################
+# Map logics to BRAMs
+#########################
+memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
+techmap -map ${YOSYS_BRAM_MAP_VERILOG}
+opt -fast -mux_undef -undriven -fine
+memory_map
+opt -undriven -fine
+
+#########################
+# Map pmuxes to muxes
+#########################
+techmap -map +/pmux2mux.v
+
+#########################
+# Map flip-flops
+#########################
+techmap -map ${YOSYS_DFF_MAP_VERILOG}
+opt_expr -mux_undef
+simplemap
+opt_expr
+opt_merge
+opt_rmdff
+opt_clean
+opt
+
+#########################
+# Map LUTs
+#########################
+abc -lut ${LUT_SIZE}
+
+#########################
+# Check and show statisitics
+#########################
+hierarchy -check
+stat
+
+#########################
+# Output netlists
+#########################
+opt_clean -purge
+write_blif ${OUTPUT_BLIF}
diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml
new file mode 100644
index 000000000..95b36d41d
--- /dev/null
+++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml
@@ -0,0 +1,62 @@
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
+LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
+LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+
+CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
+CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
+
+CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
+
+
+
+################# Adder Delays #################
+
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
+
+ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
+ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
+
+
+
+################# MULT18 Delays #################
+
+MULT18_A2Y_DELAY_MAX: 1.523e-9
+MULT18_A2Y_DELAY_MIN: 0.776e-9
+MULT18_B2Y_DELAY_MAX: 1.523e-9
+MULT18_B2Y_DELAY_MIN: 0.776e-9
+MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE
+MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE
+MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE
+
+
+
+################# BRAM Delays #################
+
+DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
+
+MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
+MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
+MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12
+MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12
+MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12
+BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12
\ No newline at end of file
diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml
new file mode 100644
index 000000000..4d1136b15
--- /dev/null
+++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml
@@ -0,0 +1,47 @@
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
+LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
+LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+
+CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
+CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
+
+CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
+
+
+
+################# Adder Delays #################
+
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
+
+ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
+ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
+
+
+
+################# BRAM Delays #################
+
+DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
+
+MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
+MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
+MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12
+MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12
+MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12
+BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12
\ No newline at end of file
diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml
new file mode 100644
index 000000000..a2af36f56
--- /dev/null
+++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml
@@ -0,0 +1,44 @@
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
+LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
+LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+
+CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
+CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
+
+CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
+
+
+
+################# Adder Delays #################
+
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
+
+ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
+ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
+
+
+
+################# MULT18 Delays #################
+
+MULT18_A2Y_DELAY_MAX: 1.523e-9
+MULT18_A2Y_DELAY_MIN: 0.776e-9
+MULT18_B2Y_DELAY_MAX: 1.523e-9
+MULT18_B2Y_DELAY_MIN: 0.776e-9
+MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE
+MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE
+MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE
\ No newline at end of file
diff --git a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml
index 31061e930..dd08b1e63 100644
--- a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml
+++ b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml
@@ -38,10 +38,10 @@ CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
 
 ################# Adder Delays #################
 
-ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9
-ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9
-ADDER_LUT4_IN2OUT_DELAY: 1.21e-9
-ADDER_LUT4_IN2COUT_DELAY: 1.21e-9
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
 
 ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
 ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml
new file mode 100644
index 000000000..e989e9341
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml
@@ -0,0 +1,702 @@
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut4">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut3_out"/>
+        <port name="lut4_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[3:0] clb.I[5:0]</loc>
+        <loc side="bottom">clb.cout clb.O[7:4] clb.I[11:6]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="7"/>
+      <input name="raddr" num_pins="7"/>
+      <input name="d_in" num_pins="8"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="8"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
+    <fixed_layout name="3x2" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disable_packing="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="${INPAD_DELAY}" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="${OUTPAD_DELAY}" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disable_packing="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
+                <input name="in" num_pins="4"/>
+                <output name="lut3_out" num_pins="2"/>
+                <output name="lut4_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
+                <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="fabric.cout"/>
+              <direct name="direct4" input="frac_logic.out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct5" input="frac_logic.out[1:1]" output="adder[0:0].b"/>
+              <complete name="direct6" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="frac_logic.out[0:0] adder[0].cout" output="ff[0:0].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
+                <delay_constant max="45e-12" in_port="adder[0].cout" out_port="ff[0:0].D"/>
+              </mux>
+              <mux name="mux2" input="frac_logic.out[1:1] adder[0].sumout" output="ff[1:1].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
+                <delay_constant max="45e-12" in_port="adder[0].sumout" out_port="ff[1:1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].cout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="adder[0].cout frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux4" input="adder[0].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 3-LUT mode definition begin -->
+        <mode name="n2_lut3">
+          <pb_type name="lut3inter" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble3" num_pb="2">
+              <input name="in" num_pins="3"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="3" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
+                <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
+              <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
+              <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
+              <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
+            <direct name="direct2" input="lut3inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 3-LUT mode definition end -->
+        <!-- BEGIN arithmetic mode of dual lut3 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut3" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="3" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <complete name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[2:0]" output="lut3[0:0].in[2:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[2:0]" output="lut3[1:1].in[2:0]"/>
+              <direct name="lut_to_add1" input="lut3[0:0].out" output="adder.a">
+              </direct>
+              <direct name="lut_to_add2" input="lut3[1:1].out" output="adder.b">
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="cout" input="ff[0:0].Q adder.cout" output="arithmetic.out[0:0]">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out[0:0]"/>
+                <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="arithmetic.out[0:0]"/>
+              </mux>
+              <mux name="sumout" input="ff[1:1].Q adder.sumout" output="arithmetic.out[1:1]">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out[1:1]"/>
+                <delay_constant max="45e-12" in_port="ff[1:1].Q" out_port="arithmetic.out[1:1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="arithmetic[0:0].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[0:0].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
+        <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[3:3].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[3:3].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[2:0].cout" output="fle[3:1].cin">
+          <pack_pattern name="chain" in_port="fle[2:0].cout" out_port="fle[3:1].cin"/>
+        </direct>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="7"/>
+      <input name="raddr" num_pins="7"/>
+      <input name="d_in" num_pins="8"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="8"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 128x8=1Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 1K dual-port RAM
+        -->
+      <mode name="mem_128x8_dp">
+        <pb_type name="mem_128x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="7" port_class="address"/>
+          <input name="raddr" num_pins="7" port_class="address"/>
+          <input name="d_in" num_pins="8" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="8" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_128x8_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_128x8_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_128x8_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_128x8_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_128x8_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_128x8_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_128x8_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_128x8_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_128x8_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_128x8_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_128x8_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_128x8_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_128x8_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_128x8_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
index a967f67a3..2ff83dc49 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
@@ -519,12 +519,12 @@
               <input name="cin" num_pins="1"/>
               <output name="cout" num_pins="1"/>
               <output name="sumout" num_pins="1"/>
-              <delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="${ADDER_LUT4_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@@ -754,12 +754,12 @@
               <input name="cin" num_pins="1"/>
               <output name="cout" num_pins="1"/>
               <output name="sumout" num_pins="1"/>
-              <delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="${ADDER_LUT4_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
             </pb_type>
             <!-- Define multi-mode flip-flop -->
             <pb_type name="ff" num_pb="1">