diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys
new file mode 100644
index 000000000..cd7ff02b5
--- /dev/null
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys
@@ -0,0 +1,102 @@
+# Yosys synthesis script for ${TOP_MODULE}
+
+#########################
+# Parse input files
+#########################
+# Read verilog files
+${READ_VERILOG_FILE}
+# Read technology library
+read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
+
+#########################
+# Prepare for synthesis
+#########################
+# Identify top module from hierarchy
+hierarchy -check -top ${TOP_MODULE}
+# - Convert process blocks to AST
+proc
+# Flatten all the gates/primitives
+flatten
+# Identify tri-state buffers from 'z' signal in AST
+# with follow-up optimizations to clean up AST
+tribuf -logic
+opt_expr
+opt_clean
+# demote inout ports to input or output port
+# with follow-up optimizations to clean up AST
+deminout
+opt
+
+opt_expr
+opt_clean
+check
+opt
+wreduce -keepdc
+peepopt
+pmuxtree
+opt_clean
+
+########################
+# Map multipliers
+# Inspired from synth_xilinx.cc
+#########################
+# Avoid merging any registers into DSP, reserve memory port registers first
+memory_dff
+
+#########################
+# Run coarse synthesis
+#########################
+# Run a tech map with default library
+techmap
+alumacc
+share
+opt
+fsm
+# Run a quick follow-up optimization to sweep out unused nets/signals
+opt -fast
+# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
+memory -nomap
+opt_clean
+
+#########################
+# Map logics to BRAMs
+#########################
+memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
+techmap -map ${YOSYS_BRAM_MAP_VERILOG}
+opt -fast -mux_undef -undriven -fine
+memory_map
+opt -undriven -fine
+
+#########################
+# Map pmuxes to muxes
+#########################
+techmap -map +/pmux2mux.v
+
+#########################
+# Map flip-flops
+#########################
+techmap -map ${YOSYS_DFF_MAP_VERILOG}
+opt_expr -mux_undef
+simplemap
+opt_expr
+opt_merge
+opt_rmdff
+opt_clean
+opt
+
+#########################
+# Map LUTs
+#########################
+abc -lut ${LUT_SIZE}
+
+#########################
+# Check and show statisitics
+#########################
+hierarchy -check
+stat
+
+#########################
+# Output netlists
+#########################
+opt_clean -purge
+write_blif ${OUTPUT_BLIF}
diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml
new file mode 100644
index 000000000..95b36d41d
--- /dev/null
+++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml
@@ -0,0 +1,62 @@
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
+LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
+LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+
+CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
+CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
+
+CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
+
+
+
+################# Adder Delays #################
+
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
+
+ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
+ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
+
+
+
+################# MULT18 Delays #################
+
+MULT18_A2Y_DELAY_MAX: 1.523e-9
+MULT18_A2Y_DELAY_MIN: 0.776e-9
+MULT18_B2Y_DELAY_MAX: 1.523e-9
+MULT18_B2Y_DELAY_MIN: 0.776e-9
+MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE
+MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE
+MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE
+
+
+
+################# BRAM Delays #################
+
+DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
+
+MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
+MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
+MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12
+MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12
+MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12
+BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12
\ No newline at end of file
diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml
new file mode 100644
index 000000000..4d1136b15
--- /dev/null
+++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml
@@ -0,0 +1,47 @@
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
+LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
+LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+
+CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
+CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
+
+CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
+
+
+
+################# Adder Delays #################
+
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
+
+ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
+ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
+
+
+
+################# BRAM Delays #################
+
+DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
+
+MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
+MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
+MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12
+MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12
+MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12
+BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12
\ No newline at end of file
diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml
new file mode 100644
index 000000000..a2af36f56
--- /dev/null
+++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml
@@ -0,0 +1,44 @@
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
+LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
+LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
+
+CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
+CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
+
+CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
+
+
+
+################# Adder Delays #################
+
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
+
+ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
+ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
+
+
+
+################# MULT18 Delays #################
+
+MULT18_A2Y_DELAY_MAX: 1.523e-9
+MULT18_A2Y_DELAY_MIN: 0.776e-9
+MULT18_B2Y_DELAY_MAX: 1.523e-9
+MULT18_B2Y_DELAY_MIN: 0.776e-9
+MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE
+MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE
+MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE
+MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE
\ No newline at end of file
diff --git a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml
index 31061e930..dd08b1e63 100644
--- a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml
+++ b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml
@@ -38,10 +38,10 @@ CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
################# Adder Delays #################
-ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9
-ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9
-ADDER_LUT4_IN2OUT_DELAY: 1.21e-9
-ADDER_LUT4_IN2COUT_DELAY: 1.21e-9
+ADDER_CIN2OUT_DELAY: 1.21e-9
+ADDER_CIN2COUT_DELAY: 1.21e-9
+ADDER_IN2OUT_DELAY: 1.21e-9
+ADDER_IN2COUT_DELAY: 1.21e-9
ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml
new file mode 100644
index 000000000..e989e9341
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml
@@ -0,0 +1,702 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ clb.clk
+ clb.cin
+ clb.O[3:0] clb.I[5:0]
+ clb.cout clb.O[7:4] clb.I[11:6]
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 1 1 1 1
+ 1 1 1 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
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+
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+
+
+
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+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 235e-12
+ 235e-12
+ 235e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 195e-12
+ 195e-12
+ 195e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
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+
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+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
index a967f67a3..2ff83dc49 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
@@ -519,12 +519,12 @@
-
-
-
-
-
-
+
+
+
+
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+
@@ -754,12 +754,12 @@
-
-
-
-
-
-
+
+
+
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+
+