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bug fixing for heterogeneous FPGAs

This commit is contained in:
tangxifan 2019-11-05 20:24:03 -07:00
parent 066962fbb9
commit 6c04b8d959
2 changed files with 5 additions and 5 deletions
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8
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp
View File

@ -684,16 +684,16 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager,
* FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then use is_cb_exist()
*/
if ( TOP == side_manager.get_side() || LEFT == side_manager.get_side() ) {
if ( (TRUE != is_cb_exist(cb_type, module_gsb_cb_coordinate.get_x(), module_gsb_cb_coordinate.get_y()))
if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)))
|| (true != rr_gsb.is_cb_exist(cb_type))) {
continue;
}
}
if ( RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side() ) {
const RRGSB& adjancent_gsb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate);
if ( (TRUE != is_cb_exist(cb_type, module_gsb_cb_coordinate.get_x(), module_gsb_cb_coordinate.get_y()))
|| (true != adjancent_gsb.is_cb_exist(cb_type))) {
const RRGSB& adjacent_gsb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate);
if ( (TRUE != is_cb_exist(cb_type, adjacent_gsb.get_cb_x(cb_type), adjacent_gsb.get_cb_y(cb_type)))
|| (true != adjacent_gsb.is_cb_exist(cb_type))) {
continue;
}
}

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -4064,7 +4064,7 @@ void print_verilog_flatten_connection_block_modules(ModuleManager& module_manage
* We will skip those modules
*/
const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy);
if ( (TRUE != is_cb_exist(CHANX, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)))
if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type)))
|| (true != rr_gsb.is_cb_exist(cb_type))) {
continue;
}