From 6c04b8d9591e8371101d892e020c764774bbe580 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 5 Nov 2019 20:24:03 -0700 Subject: [PATCH] bug fixing for heterogeneous FPGAs --- .../vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp | 8 ++++---- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index a8a5d66e9..683b5138d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -684,16 +684,16 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager, * FOr RIGHT and BOTTOM side, find the adjacent RRGSB and then use is_cb_exist() */ if ( TOP == side_manager.get_side() || LEFT == side_manager.get_side() ) { - if ( (TRUE != is_cb_exist(cb_type, module_gsb_cb_coordinate.get_x(), module_gsb_cb_coordinate.get_y())) + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) || (true != rr_gsb.is_cb_exist(cb_type))) { continue; } } if ( RIGHT == side_manager.get_side() || BOTTOM == side_manager.get_side() ) { - const RRGSB& adjancent_gsb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); - if ( (TRUE != is_cb_exist(cb_type, module_gsb_cb_coordinate.get_x(), module_gsb_cb_coordinate.get_y())) - || (true != adjancent_gsb.is_cb_exist(cb_type))) { + const RRGSB& adjacent_gsb = L_device_rr_gsb.get_gsb(module_gsb_cb_coordinate); + if ( (TRUE != is_cb_exist(cb_type, adjacent_gsb.get_cb_x(cb_type), adjacent_gsb.get_cb_y(cb_type))) + || (true != adjacent_gsb.is_cb_exist(cb_type))) { continue; } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 2c995e864..12afb3a2e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -4064,7 +4064,7 @@ void print_verilog_flatten_connection_block_modules(ModuleManager& module_manage * We will skip those modules */ const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - if ( (TRUE != is_cb_exist(CHANX, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) + if ( (TRUE != is_cb_exist(cb_type, rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type))) || (true != rr_gsb.is_cb_exist(cb_type))) { continue; }