refactored counting config bits for circuit model and update Verilog generation for primitive pb_types

vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp

@@ -91,3 +91,101 @@ std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary&
 
   return regular_sram_ports;
 }
+
+/********************************************************************
+ * Find the number of shared configuration bits for a ReRAM circuit 
+ * TODO: this function is subjected to be changed due to ReRAM-based SRAM cell design!!!
+ *******************************************************************/
+static 
+size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                                const CircuitModelId& rram_model,
+                                                const e_sram_orgz& sram_orgz_type) {
+  size_t num_shared_config_bits = 0;
+
+  /* Branch on the organization of configuration protocol */ 
+  switch (sram_orgz_type) {
+  case SPICE_SRAM_STANDALONE:
+  case SPICE_SRAM_SCAN_CHAIN:
+    break;
+  case SPICE_SRAM_MEMORY_BANK: {
+    /* Find BL/WL ports */
+    std::vector<CircuitPortId> blb_ports = circuit_lib.model_ports_by_type(rram_model, SPICE_MODEL_PORT_BLB);
+    for (auto blb_port : blb_ports) {
+      num_shared_config_bits = std::max((int)num_shared_config_bits, (int)circuit_lib.port_size(blb_port) - 1);
+    }
+    break;
+  }    
+  default:
+    vpr_printf(TIO_MESSAGE_ERROR,
+               "(File:%s,[LINE%d]) Invalid type of SRAM organization!\n",
+               __FILE__, __LINE__);
+    exit(1);
+  }
+
+  return num_shared_config_bits;
+}
+
+/********************************************************************
+ * A generic function to find the number of shared configuration bits 
+ * for circuit model
+ * It will return 0 for CMOS circuits 
+ * It will return the maximum shared configuration bits across ReRAM models
+ *
+ * Note: This function may give WRONG results when all the SRAM ports
+ * are not properly linked to its circuit models!
+ * So, it should be called after the SRAM linking is done!!!
+ *
+ * IMPORTANT: This function should NOT be used to find the number of shared configuration bits
+ * for a multiplexer, because the multiplexer size is determined during 
+ * the FPGA architecture generation (NOT during the XML parsing). 
+ *******************************************************************/
+size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                           const CircuitModelId& circuit_model,
+                                           const e_sram_orgz& sram_orgz_type) {
+  size_t num_shared_config_bits = 0;
+
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM);
+  for (auto sram_port : sram_ports) {
+    CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port);
+    VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) );
+
+    /* Depend on the design technolgy of SRAM model, the number of configuration bits will be different */
+    switch (circuit_lib.design_tech_type(sram_model)) {
+    case SPICE_MODEL_DESIGN_CMOS: 
+      /* CMOS circuit do not need shared configuration bits */
+      break;
+    case SPICE_MODEL_DESIGN_RRAM: 
+       /* RRAM circuit do need shared configuration bits, but it is subjected to the largest one among different SRAM models */
+       num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, sram_orgz_type));
+       break;
+    default:
+      vpr_printf(TIO_MESSAGE_ERROR,
+                 "(File:%s,[LINE%d]) Invalid design technology for SRAM model!\n",
+                 __FILE__, __LINE__);
+      exit(1);
+    }
+  } 
+
+  return num_shared_config_bits;
+}
+
+/********************************************************************
+ * A generic function to find the number of configuration bits 
+ * for circuit model
+ * It will sum up the sizes of all the sram ports 
+ * 
+ * IMPORTANT: This function should NOT be used to find the number of configuration bits
+ * for a multiplexer, because the multiplexer size is determined during 
+ * the FPGA architecture generation (NOT during the XML parsing). 
+ *******************************************************************/
+size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model) {
+  size_t num_config_bits = 0;
+
+  std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM);
+  for (auto sram_port : sram_ports) {
+    num_config_bits += circuit_lib.port_size(sram_port); 
+  } 
+
+  return num_config_bits;
+}

vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h

@@ -8,6 +8,7 @@
 /* Standard header files required go first */
 
 #include <vector>
+#include "spice_types.h"
 #include "circuit_library.h"
 
 std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
@@ -16,4 +17,11 @@ std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circu
 std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
                                                            const CircuitModelId& circuit_model);
 
+size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
+                                           const CircuitModelId& circuit_model,
+                                           const e_sram_orgz& sram_orgz_type);
+
+size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
+                                    const CircuitModelId& circuit_model);
+
 #endif

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp

@@ -9,6 +9,7 @@
 /* Header files from external libs */
 #include "util.h"
 #include "vtr_assert.h"
+#include "circuit_library_utils.h"
 
 /* Header files for VPR */
 #include "vpr_types.h"
@@ -116,9 +117,33 @@ void print_verilog_primitive_block(std::fstream& fp,
   add_pb_type_ports_to_module_manager(module_manager, primitive_module, primitive_pb_graph_node->pb_type); 
 
   /* Add configuration ports */
-  /* TODO: Shared SRAM ports*/
+  /* Shared SRAM ports*/
-  /* TODO: Regular (independent) SRAM ports */
+  size_t num_shared_config_bits = find_circuit_num_shared_config_bits(circuit_lib, primitive_model, cur_sram_orgz_info->type);
-  /* TODO: SRAM ports for formal verfiication */
+  if (0 < num_shared_config_bits) {
+    /* Check: this SRAM organization type must be memory-bank ! */
+    VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type );
+    /* Generate a list of ports */
+    add_reserved_sram_ports_to_module_manager(module_manager, primitive_module, 
+                                              num_shared_config_bits); 
+  }
+
+  /* TODO: this should be added to the cur_sram_orgz_info !!! */
+  t_spice_model* mem_model = NULL;
+  get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model);
+  CircuitModelId sram_model = circuit_lib.model(mem_model->name);  
+  VTR_ASSERT(CircuitModelId::INVALID() != sram_model);
+
+  /* Regular (independent) SRAM ports */
+  size_t num_config_bits = find_circuit_num_config_bits(circuit_lib, primitive_model);
+  if (0 < num_config_bits) {
+    add_sram_ports_to_module_manager(module_manager, primitive_module,
+                                     circuit_lib, sram_model, cur_sram_orgz_info->type,
+                                     num_config_bits);
+    /* Add ports only visible during formal verification to the module */
+    add_formal_verification_sram_ports_to_module_manager(module_manager, primitive_module, circuit_lib, sram_model, 
+                                                         std::string(verilog_formal_verification_preproc_flag),
+                                                         num_config_bits);
+  }
 
   /* Print the module definition for the top-level Verilog module of physical block */
   print_verilog_module_declaration(fp, module_manager, primitive_module);