diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index 2b4fd94f2..d2e41f549 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -113,6 +113,7 @@ std::string generate_mux_subckt_name(const CircuitLibrary& circuit_lib, std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& branch_mux_size, + const size_t& branch_mem_size, const std::string& postfix) { /* If the tgate circuit model of this MUX is a MUX2 standard cell, * the mux_subckt name will be the name of the standard cell @@ -122,7 +123,13 @@ std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, VTR_ASSERT (CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(subckt_model)); return circuit_lib.model_name(subckt_model); } - std::string branch_postfix = postfix + "_size" + std::to_string(branch_mux_size); + + /* Include memory size as a second unique signature for the branch module + * This is due to some branch modules have the same input sizes but different memory sizes + */ + std::string branch_postfix = postfix + + "_input" + std::to_string(branch_mux_size) + + "_mem" + std::to_string(branch_mem_size); std::string module_name = circuit_lib.model_name(circuit_model); if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(circuit_model)) { diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h index 27ba308f1..a3cfac08c 100644 --- a/openfpga/src/base/openfpga_naming.h +++ b/openfpga/src/base/openfpga_naming.h @@ -44,6 +44,7 @@ std::string generate_mux_subckt_name(const CircuitLibrary& circuit_lib, std::string generate_mux_branch_subckt_name(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& branch_mux_size, + const size_t& branch_mem_size, const std::string& posfix); std::string generate_mux_local_decoder_subckt_name(const size_t& addr_size, diff --git a/openfpga/src/fabric/build_mux_modules.cpp b/openfpga/src/fabric/build_mux_modules.cpp index 1a28308ed..fcf0db026 100644 --- a/openfpga/src/fabric/build_mux_modules.cpp +++ b/openfpga/src/fabric/build_mux_modules.cpp @@ -334,7 +334,7 @@ void build_mux_branch_module(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const CircuitModelId& mux_model, const MuxGraph& mux_graph) { - std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_graph.num_inputs(), MUX_BASIS_MODULE_POSTFIX); + std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(), MUX_BASIS_MODULE_POSTFIX); /* Skip the module building if it is already there */ if (module_manager.valid_module_id(module_manager.find_module(module_name))) { @@ -574,9 +574,19 @@ void build_cmos_mux_module_tgate_multiplexing_structure(ModuleManager& module_ma */ size_t branch_size = mux_graph.node_in_edges(node).size(); - /* Instanciate the branch module which is a tgate-based module - */ - std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, branch_size, MUX_BASIS_MODULE_POSTFIX); + /* Get the mems in the branch circuits */ + std::vector mems; + for (const auto& edge : mux_graph.node_in_edges(node)) { + /* Get the mem control the edge */ + MuxMemId mem = mux_graph.find_edge_mem(edge); + /* Add the mem if it is not in the list */ + if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { + mems.push_back(mem); + } + } + + /* Instanciate the branch module which is a tgate-based module */ + std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, branch_size, mems.size(), MUX_BASIS_MODULE_POSTFIX); /* Get the moduleId for the submodule */ ModuleId branch_module_id = module_manager.find_module(branch_module_name); /* We must have one */ @@ -614,17 +624,6 @@ void build_cmos_mux_module_tgate_multiplexing_structure(ModuleManager& module_ma module_nets_by_level[output_node_level][output_node_index_at_level] = branch_net; /* Wire the branch module memory ports to the nets of MUX memory ports */ - /* Get the mems in the branch circuits */ - std::vector mems; - for (const auto& edge : mux_graph.node_in_edges(node)) { - /* Get the mem control the edge */ - MuxMemId mem = mux_graph.find_edge_mem(edge); - /* Add the mem if it is not in the list */ - if (mems.end() == std::find(mems.begin(), mems.end(), mem)) { - mems.push_back(mem); - } - } - /* Get mem/mem_inv ports of branch module */ ModulePortId branch_module_mem_port_id = module_manager.find_module_port(branch_module_id, std::string("mem")); BasicPort branch_module_mem_port = module_manager.module_port(branch_module_id, branch_module_mem_port_id); diff --git a/openfpga/src/fpga_spice/spice_mux.cpp b/openfpga/src/fpga_spice/spice_mux.cpp index 02c5be81d..147387848 100644 --- a/openfpga/src/fpga_spice/spice_mux.cpp +++ b/openfpga/src/fpga_spice/spice_mux.cpp @@ -52,7 +52,7 @@ void generate_spice_mux_branch_subckt(const ModuleManager& module_manager, const CircuitModelId& mux_model, const MuxGraph& mux_graph, std::map& branch_mux_module_is_outputted) { - std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_graph.num_inputs(), SPICE_MUX_BASIS_POSTFIX); + std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(), SPICE_MUX_BASIS_POSTFIX); /* Skip outputting if the module has already been outputted */ auto result = branch_mux_module_is_outputted.find(module_name); diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index 4b4414bbe..a0fd896e2 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -584,7 +584,7 @@ void generate_verilog_mux_branch_module(ModuleManager& module_manager, const MuxGraph& mux_graph, const bool& use_explicit_port_map, std::map& branch_mux_module_is_outputted) { - std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_graph.num_inputs(), VERILOG_MUX_BASIS_POSTFIX); + std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(), VERILOG_MUX_BASIS_POSTFIX); /* Skip outputting if the module has already been outputted */ auto result = branch_mux_module_is_outputted.find(module_name); @@ -884,7 +884,7 @@ void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& modu /* Instanciate the branch module which is a tgate-based module */ - std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, branch_size, VERILOG_MUX_BASIS_POSTFIX); + std::string branch_module_name= generate_mux_branch_subckt_name(circuit_lib, circuit_model, branch_size, mems.size(), VERILOG_MUX_BASIS_POSTFIX); /* Get the moduleId for the submodule */ ModuleId branch_module_id = module_manager.find_module(branch_module_name); /* We must have one */