[Architecture] Enrich SRAM Verilog HDL for flexible set/reset support

openfpga_flow/VerilogNetlists/sram.v

@@ -42,27 +42,32 @@ output outb // Data output
 
 endmodule
 
-module sram_blwl_set(
+//-----------------------------------------------------
-input set, // Word line control signal
+// Function    : A SRAM cell with 
-input wl, // Word line control signal
+//               - an active-high set
-input bl, // Bit line control signal
+//               - a write-enable
-output out, // Data output
+//-----------------------------------------------------
-output outb // Data output
+module SRAMS(
+  input SET, // active-high set signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
 );
 
   //----- local variable need to be registered
   reg data;
 
   //----- when wl is enabled, we can read in data from bl
-  always @(bl or wl) 
+  always @(D or WE) 
   begin
-    if (1'b1 == set) begin 
+    if (1'b1 == SET) begin 
       data <= 1'b1;
-    end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
     //----- Cases to program internal memory bit 
     //----- case 1: bl = 1, wl = 1, a -> 0
       data <= 1'b1;
-    end else if ((1'b0 == bl)&&(1'b1 == wl)) begin
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
     //----- case 2: bl = 0, wl = 1, a -> 0
      data <= 1'b0;
     end 
@@ -70,39 +75,83 @@ output outb // Data output
 
 `ifndef ENABLE_FORMAL_VERIFICATION
     // Wire q_reg to Q
-    assign out = data;
+    assign Q = data;
-    assign outb = ~data;
+    assign QN = ~data;
 `else
-    assign out = 1'bZ;
+    assign Q = 1'bZ;
-    assign outb = !out;
+    assign QN = !out;
 `endif
 
 endmodule
 
-module sram_blwl_set_reset(
+//-----------------------------------------------------
-input reset, // Word line control signal
+// Function    : A SRAM cell with 
-input set, // Word line control signal
+//               - an active-low set
-input wl, // Word line control signal
+//               - a write-enable
-input bl, // Bit line control signal
+//-----------------------------------------------------
-output out, // Data output
+module SRAMSN(
-output outb // Data output
+  input SETN, // active-low set signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
 );
 
   //----- local variable need to be registered
   reg data;
 
   //----- when wl is enabled, we can read in data from bl
-  always @(bl or wl) 
+  always @(D or WE) 
   begin
-    if (1'b1 == reset) begin 
+    if (1'b0 == SETN) begin 
+      data <= 1'b1;
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+      data <= 1'b1;
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
+    //----- case 2: bl = 0, wl = 1, a -> 0
+     data <= 1'b0;
+    end 
+  end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign Q = data;
+    assign QN = ~data;
+`else
+    assign Q = 1'bZ;
+    assign QN = !out;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A SRAM cell with 
+//               - an active-high reset
+//               - a write-enable
+//-----------------------------------------------------
+module SRAMR(
+  input RST, // active-high reset signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(D or WE) 
+  begin
+    if (1'b1 == RST) begin 
       data <= 1'b0;
-    end else if (1'b1 == set) begin 
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
-      data <= 1'b1;
-    end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
     //----- Cases to program internal memory bit 
     //----- case 1: bl = 1, wl = 1, a -> 0
       data <= 1'b1;
-    end else if ((1'b0 == bl)&&(1'b1 == wl)) begin
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
     //----- case 2: bl = 0, wl = 1, a -> 0
      data <= 1'b0;
     end 
@@ -110,58 +159,150 @@ output outb // Data output
 
 `ifndef ENABLE_FORMAL_VERIFICATION
     // Wire q_reg to Q
-    assign out = data;
+    assign Q = data;
-    assign outb = ~data;
+    assign QN = ~data;
 `else
-    assign out = 1'bZ;
+    assign Q = 1'bZ;
-    assign outb = !out;
+    assign QN = !out;
 `endif
 
 endmodule
 
-
+//-----------------------------------------------------
-
+// Function    : A SRAM cell with 
-//------ Module: sram6T_blwl -----//
+//               - an active-low reset
-//------ Verilog file: sram.v -----//
+//               - a write-enable
-//------ Author: Xifan TANG -----//
+//-----------------------------------------------------
-module sram6T_blwl(
+module SRAMRN(
-//input read,
+  input RSTN, // active-low reset signal
-//input nequalize,
+  input WE, // Word line control signal as write enable
-input din, // Data input
+  input D, // Bit line control signal as data input
-output dout, // Data output
+  output Q, // Data output
-output doutb, // Data output
+  output QN // Data output
-input bl, // Bit line control signal
-input wl, // Word line control signal
-input blb // Inverted Bit line control signal
 );
+
   //----- local variable need to be registered
-  reg a;
+  reg data;
 
   //----- when wl is enabled, we can read in data from bl
-  always @(bl, wl) 
+  always @(D or WE) 
   begin
+    if (1'b0 == RSTN) begin 
+      data <= 1'b0;
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
     //----- Cases to program internal memory bit 
     //----- case 1: bl = 1, wl = 1, a -> 0
-    if ((1'b1 == bl)&&(1'b1 == wl)) begin
+      data <= 1'b1;
-      a <= 1'b1;
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
-    end 
     //----- case 2: bl = 0, wl = 1, a -> 0
-    if ((1'b0 == bl)&&(1'b1 == wl)) begin
+     data <= 1'b0;
-     a <= 1'b0;
     end 
   end
 
-  // dout is short-wired to din 
+`ifndef ENABLE_FORMAL_VERIFICATION
-  assign dout = a;
+    // Wire q_reg to Q
-  //---- doutb is always opposite to dout 
+    assign Q = data;
-  assign doutb = ~dout;
+    assign QN = ~data;
-`ifdef ENABLE_SIGNAL_INITIALIZATION
+`else
-   initial begin
+    assign Q = 1'bZ;
-     $deposit(a, $random);
+    assign QN = !out;
-   end
 `endif
+
 endmodule
 
+//-----------------------------------------------------
+// Function    : A SRAM cell with 
+//               - an active-high reset
+//               - an active-high set
+//               - a write-enable
+//-----------------------------------------------------
+module SRAMSR(
+  input RST, // active-high reset signal
+  input SET, // active-high set signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(D or WE) 
+  begin
+    if (1'b1 == RST) begin 
+      data <= 1'b0;
+    end else if (1'b1 == SET) begin 
+      data <= 1'b1;
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+      data <= 1'b1;
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
+    //----- case 2: bl = 0, wl = 1, a -> 0
+     data <= 1'b0;
+    end 
+  end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign Q = data;
+    assign QN = ~data;
+`else
+    assign Q = 1'bZ;
+    assign QN = !out;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A SRAM cell with 
+//               - an active-low reset
+//               - an active-low set
+//               - a write-enable
+//-----------------------------------------------------
+module SRAMSNRN(
+  input RSTN, // active-low reset signal
+  input SETN, // active-low set signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(D or WE) 
+  begin
+    if (1'b0 == RSTN) begin 
+      data <= 1'b0;
+    end else if (1'b0 == SETN) begin 
+      data <= 1'b1;
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+      data <= 1'b1;
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
+    //----- case 2: bl = 0, wl = 1, a -> 0
+     data <= 1'b0;
+    end 
+  end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign Q = data;
+    assign QN = ~data;
+`else
+    assign Q = 1'bZ;
+    assign QN = !out;
+`endif
+
+endmodule
+
+
 module sram6T_rram(
 input read,
 input nequalize,