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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb

This commit is contained in:
tangxifan 2019-05-28 14:53:44 -06:00
parent af91fca1e0 3da216f297
commit 6b51b42ee7
3 changed files with 10 additions and 3 deletions
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2
vpr7_x2p/vpr/ARCH/.travis_k6_N10_sram_chain_HC.xml
View File

@ -180,7 +180,7 @@
</input> </input>
</stimulate> </stimulate>
</parameters> </parameters>
<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="/research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/> <tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="/home/travis/build/LNIS-Projects/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M"> <transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/> <nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/> <pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -1033,10 +1033,13 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp) {
} }
t_rr_node* cur_rr_node = rr_sb.get_chan_node(side_manager.get_side(), itrack); t_rr_node* cur_rr_node = rr_sb.get_chan_node(side_manager.get_side(), itrack);
for (int imux = 0 ; imux < cur_rr_node->fan_in; ++imux) { for (int imux = 0 ; imux < cur_rr_node->fan_in; ++imux) {
if (1 == cur_rr_node->fan_in) {
continue;
}
if (imux == cur_rr_node->id_path) { if (imux == cur_rr_node->id_path) {
fprintf(fp, "#"); // comments out if the node is active fprintf(fp, "#"); // comments out if the node is active
} }
//if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux); //if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux);
fprintf(fp, "set_disable_timing %s[%d]\n", fprintf(fp, "set_disable_timing %s[%d]\n",
cur_rr_node->name_mux, imux); cur_rr_node->name_mux, imux);
} }
@ -1070,10 +1073,13 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp, int LL_nx, int LL_ny
if (OUT_PORT == cur_sb_info->chan_rr_node_direction[side][itrack]) { if (OUT_PORT == cur_sb_info->chan_rr_node_direction[side][itrack]) {
cur_rr_node = cur_sb_info->chan_rr_node[side][itrack]; cur_rr_node = cur_sb_info->chan_rr_node[side][itrack];
for (imux = 0 ; imux < cur_rr_node-> fan_in; imux++) { for (imux = 0 ; imux < cur_rr_node-> fan_in; imux++) {
if (1 == cur_rr_node->fan_in) {
continue;
}
if (imux == cur_rr_node->id_path) { if (imux == cur_rr_node->id_path) {
fprintf(fp, "#"); // comments out if the node is active fprintf(fp, "#"); // comments out if the node is active
} }
//if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux); //if(cur_rr_node->name_mux == NULL) assert (NULL != cur_rr_node->name_mux);
fprintf(fp, "set_disable_timing %s[%d]\n", fprintf(fp, "set_disable_timing %s[%d]\n",
cur_rr_node->name_mux, imux); cur_rr_node->name_mux, imux);
} }

1
vpr7_x2p/vpr/go_fpga_verilog.sh
View File

@ -34,6 +34,7 @@ set vpr_route_chan_width = 200
#make -j32 #make -j32
# Remove previous designs # Remove previous designs
rm -rf $verilog_output_dirpath/$verilog_output_dirname rm -rf $verilog_output_dirpath/$verilog_output_dirname
rm -rf $verilog_output_dirpath/$verilog_output_dirname\_compact
# Run VPR # Run VPR
#valgrind #valgrind