diff --git a/.travis/script.sh b/.travis/script.sh index fa9e95ea8..37e96e1a8 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,5 +18,5 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing --maxthreads 2 +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 2 end_section "OpenFPGA.TaskTun" diff --git a/docs/source/arch_lang/figures/point2point_example.png b/docs/source/arch_lang/figures/point2point_example.png new file mode 100644 index 000000000..a63df9d38 Binary files /dev/null and b/docs/source/arch_lang/figures/point2point_example.png differ diff --git a/docs/source/arch_lang/figures/point2point_truthtable.png b/docs/source/arch_lang/figures/point2point_truthtable.png new file mode 100644 index 000000000..d81bab338 Binary files /dev/null and b/docs/source/arch_lang/figures/point2point_truthtable.png differ diff --git a/docs/source/arch_lang/index.rst b/docs/source/arch_lang/index.rst index bafd8f6e2..86edc3886 100644 --- a/docs/source/arch_lang/index.rst +++ b/docs/source/arch_lang/index.rst @@ -8,6 +8,8 @@ Extended Architecture Description Language :maxdepth: 2 generality + + interconnect spice_sim_setting diff --git a/docs/source/arch_lang/interconnect.rst b/docs/source/arch_lang/interconnect.rst new file mode 100644 index 000000000..a6542ccb5 --- /dev/null +++ b/docs/source/arch_lang/interconnect.rst @@ -0,0 +1,94 @@ +Interconnection extensions +========================== + +This section introduces extensions on the architecture description file about existing interconnection description. + +Directlist +---------- + +The original direct connections in the directlist section are documented here_. Its description is given below: + +.. _here: http://docs.verilogtorouting.org/en/latest/arch/reference/?highlight=directlist#direct-inter-block-connections + +.. code-block:: xml + + + + + +.. note:: These options are required + +Our extension include three more options: + +.. code-block:: xml + + + + + +.. note:: these options are optional. However, if *interconnection_type* is set *x_dir* and *y_dir* are required. + +* **interconnection_type**: [``NONE`` | ``column`` | ``row``], specifies if it applies on a column or a row ot if it doesn't apply. + +* **x_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives: + + * x_dir="positive": + + * interconnection_type="column": a column will be connected to a column on the **right**, if it exists. + + * interconnection_type="row": the most on the **right** cell from a row connection will connect the most on the **left** cell of next row, if it exists. + + * x_dir="negative": + + * interconnection_type="column": a column will be connected to a column on the **left**, if it exists. + + * interconnection_type="row": the most on the **left** cell from a row connection will connect the most on the **right** cell of next row, if it exists. + +* **y_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives: + + * y_dir="positive": + + * interconnection_type="column": the **bottom** cell of a column will be connected to the next column **top** cell, if it exists. + + * interconnection_type="row": a row will be connected on an **above** row, if it exists. + + * y_dir="negative": + + * interconnection_type="column": the **top** cell of a column will be connected to the next column **bottom** cell, if it exists. + + * interconnection_type="row": a row will be connected on a row **below**, if it exists. + +Example +------- + +For this example, we will study a scan-chain implementation. The description could be: + +.. code-block:: xml + + + + + +:numref:`fig_p2p_exple` is the graphical representation of the above scan-chain description on a 4x4 FPGA. + +.. _fig_p2p_exple: + +.. figure:: ./figures/point2point_example.png + + An example of scan-chain implementation + + +In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB. + +Truth table +----------- + +A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below. + +:numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate. + +.. _fig_p2p_trtable: + +.. figure:: ./figures/point2point_truthtable.png + + Point to point truth table diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index 4a7893a83..c54ce8403 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -62,3 +62,4 @@ vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= #vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= + diff --git a/openfpga_flow/tasks/explicit_verilog/config/task.conf b/openfpga_flow/tasks/explicit_verilog/config/task.conf new file mode 100644 index 000000000..be4320161 --- /dev/null +++ b/openfpga_flow/tasks/explicit_verilog/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif + +[SYNTHESIS_PARAM] +bench0_top = test_modes +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT] +fix_route_chan_width=300 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_x2p_compact_routing_hierarchy= +vpr_fpga_verilog_explicit_mapping= +end_flow_with_test= diff --git a/tutorials/building.md b/tutorials/building.md index 7525493a4..a91448b36 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -1,7 +1,6 @@ # How to build? ## Dependencies - OpenFPGA requires all the following dependencies: - autoconf - automake @@ -39,10 +38,9 @@ OpenFPGA requires all the following dependencies: - qt5-default ## Docker - -If all these dependancies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). To ease customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command: +If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command: - docker run lnis/open_fpga:release
-*Warning: This command is for quick testing. If you want to conserve your work you should certainly use other options as "-v".* +*Warning: This command is for quick testing. If you want to conserve your work, you should certainly use other options, such as "-v".* Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands: - docker build . -t open_fpga @@ -50,8 +48,7 @@ Otherwise, a container where you can build OpenFPGA yourself can be created with [*docker download link*](https://www.docker.com/products/docker-desktop) ## Building - -To build the tool you have to go in OpenFPGA folder and do: +To build the tool, go in the OpenFPGA folder and do: - mkdir build && cd build - cmake .. -DCMAKE_BUILD_TYPE=debug - make (*WARNING using docker you cannot use "make -j", errors will happen*) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index d687a1468..9413e02fa 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -3072,6 +3072,18 @@ bool DeviceRRGSB::validate_coordinator(DeviceCoordinator& coordinator) const { return true; } +/* Validate if the (x,y) is the range of this device, but takes into consideration that edges are 1 off */ +bool DeviceRRGSB::validate_coordinator_edge(DeviceCoordinator& coordinator) const { + if (coordinator.get_x() >= rr_gsb_.capacity() + 1) { + return false; + } + if (coordinator.get_y() >= rr_gsb_[coordinator.get_x()].capacity() + 1) { + return false; + } + return true; +} + + /* Validate if the index in the range of unique_mirror vector*/ bool DeviceRRGSB::validate_side(enum e_side side) const { Side side_manager(side); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index 6dd2437fb..54348046a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -371,6 +371,7 @@ class DeviceRRGSB { void clear_segment_ids(); private: /* Validators */ bool validate_coordinator(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device */ + bool validate_coordinator_edge(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device but takes into consideration the fact that edges are 1 off */ bool validate_side(enum e_side side) const; /* validate if side is in the range of unique_side_module_ */ bool validate_sb_unique_module_index(size_t index) const; /* Validate if the index in the range of unique_mirror vector*/ bool validate_cb_unique_module_index(t_rr_type cb_type, size_t index) const; /* Validate if the index in the range of unique_mirror vector*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 28056e1c1..96aea8d43 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -789,14 +789,15 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { Side side_manager(side); DeviceCoordinator chan_coordinator = rr_sb.get_side_block_coordinator(side_manager.get_side()); + DeviceCoordinator unique_chan_coordinator = unique_mirror.get_side_block_coordinator(side_manager.get_side()); fprintf(fp, "//----- %s side channel ports-----\n", side_manager.c_str()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { if (true == is_explicit_mapping) { fprintf(fp, ".%s(", - gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), - chan_coordinator.get_x(), chan_coordinator.get_y(), itrack, - rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + gen_verilog_routing_channel_one_pin_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack), + unique_chan_coordinator.get_x(), unique_chan_coordinator.get_y(), itrack, + unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack))); } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), @@ -815,6 +816,8 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow, + unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow, FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } @@ -964,6 +967,8 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), cur_ipin_node->xlow, cur_ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -1107,27 +1112,27 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { switch (rr_chan.get_node(itrack)->direction) { case INC_DIRECTION: - if (true == is_explicit_mapping) { - fprintf(fp, ".in%d (",itrack); - } + if (true == is_explicit_mapping) { + fprintf(fp, ".in%d (",itrack); + } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, OUT_PORT)); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); break; case DEC_DIRECTION: - if (true == is_explicit_mapping) { - fprintf(fp, ".out%d (",itrack); - } + if (true == is_explicit_mapping) { + fprintf(fp, ".out%d (",itrack); + } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, IN_PORT)); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); break; default: @@ -1147,27 +1152,27 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { switch (rr_chan.get_node(itrack)->direction) { case INC_DIRECTION: - if (true == is_explicit_mapping) { - fprintf(fp, ".out%d (",itrack); - } + if (true == is_explicit_mapping) { + fprintf(fp, ".out%d (",itrack); + } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, IN_PORT)); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); break; case DEC_DIRECTION: - if (true == is_explicit_mapping) { - fprintf(fp, ".in%d (",itrack); - } + if (true == is_explicit_mapping) { + fprintf(fp, ".in%d (",itrack); + } fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, OUT_PORT)); - if (true == is_explicit_mapping) { - fprintf(fp, ")"); - } + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); break; default: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c index bdfff337b..410e5d366 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c @@ -372,7 +372,7 @@ void dump_verilog_membank_one_inv_module(FILE* fp, inv_spice_model->name, inv_spice_model->prefix, instance_tag, inv_index); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, inv_spice_model, FALSE, FALSE, inv_spice_model->dump_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index f87ff45a7..4e6ec1d4a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1142,7 +1142,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s_%d_ (", cur_interc->spice_model->prefix, cur_interc->spice_model->cnt); cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Print the pin names! Input and output @@ -1278,7 +1278,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s_size%d ", cur_interc->spice_model->name, fan_in); fprintf(fp, "%s_size%d_%d_ (", cur_interc->spice_model->prefix, fan_in, cur_interc->spice_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Inputs */ @@ -1874,7 +1874,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, } else { if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model, - FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), + FALSE)) { + fprintf(fp, ",\n"); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index a487a5677..a5d4012cc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -123,7 +123,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -228,13 +228,17 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, } /* Call the subckt*/ - fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + if (0 == strcmp(verilog_model->name,port_prefix)) { + fprintf(fp, "%s %s_logic_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } else { + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model * Disable recursive here ! */ /*if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {*/ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } @@ -535,7 +539,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, formatted_subckt_prefix, cur_pb_type->name); fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ @@ -610,14 +614,18 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, subckt_require_explicit_port_map = TRUE; } /* Call LUT subckt*/ - fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + if (0 == strcmp(verilog_model->name,port_prefix)) { + fprintf(fp, "%s %s_logic_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } else { + fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); + } fprintf(fp, "\n"); /* if we have to add global ports when dumping submodules of LUTs * otherwise, the port map here does not match that of submodules * Only dump the global ports belonging to a spice_model * DISABLE recursive here ! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Connect inputs*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index d784888d1..61201e9fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -755,6 +755,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping) { int height; @@ -802,7 +803,7 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, is_explicit_mapping = false; /* Both cannot be true at the same time */ } if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); + fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(unique_x, unique_y, height, side, pin_index, TRUE)); } fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); if (true == is_explicit_mapping) { @@ -1006,6 +1007,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_node), grid_x, grid_y, + 0, 0, /* No explicit mapping*/ FALSE, false); /* Do not dump the direction of the port! */ break; case CHANX: @@ -1108,6 +1110,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], grid_x, grid_y, + 0, /*Used in more recent version*/ + 0, /*Used in more recent version*/ FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ break; case CHANX: @@ -1213,7 +1217,10 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], - grid_x, grid_y, FALSE, is_explicit_mapping); + grid_x, grid_y, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ + FALSE, is_explicit_mapping); fprintf(fp, ";\n"); input_cnt++; break; @@ -1277,7 +1284,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1470,7 +1477,9 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]), - grid_x, grid_y, FALSE, false); + grid_x, grid_y, + 0,0,/*No explicit mapping */ + FALSE, false); fprintf(fp, ";\n"); input_cnt++; break; @@ -1534,7 +1543,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -2837,7 +2846,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -2876,6 +2885,8 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, + 0,/*used in more recent version*/ + 0,/*used in more recent version*/ TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2904,7 +2915,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_sb_conf_bits_lsb(), rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT, is_explicit_mapping); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -3078,6 +3089,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->opin_rr_node_grid_side[side][inode], cur_sb_info->opin_rr_node[side][inode]->xlow, cur_sb_info->opin_rr_node[side][inode]->ylow, + cur_sb_info->opin_rr_node[side][inode]->xlow, + cur_sb_info->opin_rr_node[side][inode]->ylow, TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -3326,6 +3339,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -3403,6 +3417,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of this pin */ /* End */ @@ -3529,7 +3544,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3560,6 +3575,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -3776,7 +3792,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3807,6 +3823,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ + 0,0, /*No explicit mapping */ FALSE, false); /* Do not specify the direction of port */ if (true == is_explicit_mapping) { fprintf(fp, ")"); @@ -4136,6 +4153,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, + 0,0, /*No explicit mapping */ TRUE, false); } @@ -4356,6 +4374,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0,/*Used in more recent version*/ + 0,/*Used in more recent version*/ TRUE, is_explicit_mapping); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 11bcdf070..1e12d0b45 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -22,6 +22,7 @@ void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, + int unique_x, int unique_y, /* If explicit, needs the coordinates of the mirror*/ boolean dump_port_type, bool is_explicit_mapping); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index b70163422..4311c341f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -638,6 +638,8 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, des_rr_node->xlow, des_rr_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* If src_node == des_node, this is a metal wire */ @@ -723,6 +725,8 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, mirror_ipin_node->xlow, mirror_ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* If src_node == des_node, this is a metal wire */ @@ -1769,6 +1773,8 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), ipin_node->xlow, ipin_node->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } @@ -1827,6 +1833,8 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, + 0, /*explicit mapping is false*/ + 0, /*explicit mapping is false*/ FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 40095d8a8..3a2723ec2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -170,7 +170,7 @@ void dump_verilog_cmos_mux_one_basis_module(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -288,7 +288,7 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -391,7 +391,7 @@ void dump_verilog_rram_mux_one_basis_module_structural(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -457,7 +457,7 @@ void dump_verilog_rram_mux_one_basis_module(FILE* fp, /* Print the port list and definition */ fprintf(fp, "module %s (\n", mux_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Port list */ @@ -797,7 +797,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map), TRUE)) { fprintf(fp, ",\n"); } if (true == use_explicit_port_map) { @@ -840,7 +840,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } else { assert (SPICE_MODEL_PASSGATE == tgate_spice_model->type); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -894,7 +894,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, spice_model.lut_intermediate_buffer->spice_model_name, nextlevel, out_idx); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.lut_intermediate_buffer->spice_model, FALSE, FALSE, spice_model.lut_intermediate_buffer->spice_model->dump_explicit_port_map, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -1024,7 +1024,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1073,7 +1073,7 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } if (true == is_explicit_mapping) { @@ -1181,7 +1181,7 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, - my_bool_to_boolean(is_explicit_mapping))) { + my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); @@ -1346,7 +1346,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.name, mux_size); fprintf(fp, "module %s_mux(\n", spice_model.name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print input ports*/ @@ -1428,7 +1428,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.input_buffer->spice_model_name, spice_model.input_buffer->spice_model_name, i); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -1494,7 +1494,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, spice_model.output_buffer->spice_model_name, iport, ipin); /* subckt name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* check */ @@ -1604,7 +1604,7 @@ void dump_verilog_rram_mux_tree_structure(FILE* fp, /* Each basis mux2to1: svdd sgnd */ fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */ @@ -1684,7 +1684,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(\n", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* inputs */ @@ -1702,7 +1702,7 @@ void dump_verilog_rram_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ @@ -1748,7 +1748,7 @@ void dump_verilog_rram_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); @@ -1833,7 +1833,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, gen_verilog_one_mux_module_name(&spice_model, mux_size)); } /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print input ports*/ @@ -1889,7 +1889,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, spice_model.input_buffer->spice_model_name, spice_model.input_buffer->spice_model_name, i); /* Given name*/ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -1952,7 +1952,7 @@ void dump_verilog_rram_mux_submodule(FILE* fp, spice_model.output_buffer->spice_model_name, spice_model.output_buffer->spice_model_name); /* subckt name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, spice_model.output_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -2336,6 +2336,74 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, return; } +void dump_verilog_wire_module(FILE* fp, + char* wire_subckt_name, + t_spice_model verilog_model) { + int num_input_port = 0; + int num_output_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + + /* Ensure a valid file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File handler.\n", + __FILE__, __LINE__); + exit(1); + } + /* Check the wire model*/ + assert(NULL != verilog_model.wire_param); + assert(0 < verilog_model.wire_param->level); + /* Find the input port, output port*/ + input_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(&verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + + /* Asserts*/ + assert(1 == num_input_port); + assert(1 == num_output_port); + assert(1 == input_port[0]->size); + assert(1 == output_port[0]->size); + /* print the spice model*/ + fprintf(fp, "//-----Wire module, verilog_model_name=%s -----\n", verilog_model.name); + switch (verilog_model.type) { + case SPICE_MODEL_CHAN_WIRE: + /* Add an output at middle point for connecting CB inputs */ + fprintf(fp, "module %s (\n", wire_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "input wire %s, output wire %s, output wire mid_out);\n", + input_port[0]->prefix, output_port[0]->prefix); + fprintf(fp, "\tassign %s = %s;\n", output_port[0]->prefix, input_port[0]->prefix); + fprintf(fp, "\tassign mid_out = %s;\n", input_port[0]->prefix); + break; + case SPICE_MODEL_WIRE: + /* Add an output at middle point for connecting CB inputs */ + fprintf(fp, "module %s (\n", + wire_subckt_name); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &verilog_model, TRUE, FALSE, FALSE, TRUE)) { + fprintf(fp, ",\n"); + } + fprintf(fp, "input wire %s, output wire %s);\n", + input_port[0]->prefix, output_port[0]->prefix); + /* Direct shortcut */ + fprintf(fp, "\t\tassign %s = %s;\n", output_port[0]->prefix, input_port[0]->prefix); + break; + default: + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of spice_model! Expect [chan_wire|wire].\n", + __FILE__, __LINE__); + exit(1); + } + + /* Finish*/ + fprintf(fp, "endmodule\n"); + fprintf(fp, "//-----END Wire module, verilog_model_name=%s -----\n", verilog_model.name); + fprintf(fp, "\n"); + + return; +} + /* Dump one module of a LUT */ static void dump_verilog_submodule_one_lut(FILE* fp, @@ -2380,7 +2448,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, fprintf(fp, "//-----LUT module, verilog_model_name=%s -----\n", verilog_model->name); fprintf(fp, "module %s (", verilog_model->name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Print module port list */ @@ -2631,7 +2699,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, verilog_model->lut_input_buffer->spice_model->name, input_port[0]->prefix, ipin); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_buffer->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_buffer->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ @@ -2675,7 +2743,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, verilog_model->lut_input_inverter->spice_model->name, input_port[0]->prefix, ipin); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_inverter->spice_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model->lut_input_inverter->spice_model, FALSE, FALSE, TRUE, TRUE)) { fprintf(fp, ",\n"); } /* Dump explicit port map if required */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c index 256f281a9..c3df4ed95 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c @@ -187,6 +187,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, mirror_node->xlow, mirror_node->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE,is_explicit_mapping); /* Do not specify direction of port */ break; } @@ -231,6 +233,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, cur_rr_node->xlow, cur_rr_node->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE, is_explicit_mapping); /* Do not specify direction of port */ break; case CHANX: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 0bb9cff78..ad025a567 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -689,6 +689,8 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf cur_cb_info.ipin_rr_node_grid_side[side][inode], cur_cb_info.ipin_rr_node[side][inode]->xlow, cur_cb_info.ipin_rr_node[side][inode]->ylow, + 0, /*Used in newer version*/ + 0, /*Used in newer version*/ FALSE, is_explicit_mapping); /* Do not specify direction of port */ fprintf(fp, ", \n"); } @@ -836,6 +838,8 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, cur_sb_info.opin_rr_node_grid_side[side][inode], cur_sb_info.opin_rr_node[side][inode]->xlow, cur_sb_info.opin_rr_node[side][inode]->ylow, + 0, /*Used in a more recent version*/ + 0, /*Used in a more recent version*/ FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } @@ -937,7 +941,7 @@ void dump_verilog_one_clb2clb_direct(FILE* fp, fprintf(fp, "%s ", cur_direct->spice_model->name); fprintf(fp, "%s_%d_ (", cur_direct->spice_model->prefix, cur_direct->spice_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_direct->spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_direct->spice_model, FALSE, FALSE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input: Print the source grid pin */ @@ -1211,6 +1215,7 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_ FILE* fp, bool is_explicit_mapping) { int num_mem_bits = 0; + t_spice_model* ccff_mem_model = NULL; /* Check */ assert(SPICE_SRAM_SCAN_CHAIN == cur_sram_orgz_info->type); @@ -1222,6 +1227,9 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_ /* Get the total memory bits */ num_mem_bits = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + /* Get model of the configuration chain */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &ccff_mem_model); + /* Dump each Scan-chain FF */ fprintf(fp, "//------ Configuration peripheral for Scan-chain FFs -----\n"); fprintf(fp, "%s %s_0_ (\n", @@ -1239,7 +1247,8 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_ } fprintf(fp, ",\n"); if (true == is_explicit_mapping) { - fprintf(fp, ".ccff_ccff_in_local_bus ("); + fprintf(fp, ".%s_ccff_in_local_bus (", + ccff_mem_model->prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, -1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { @@ -1247,7 +1256,8 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_ } fprintf(fp, ",\n"); if (true == is_explicit_mapping) { - fprintf(fp, ".ccff_ccff_out_local_bus ("); + fprintf(fp, ".%s_ccff_out_local_bus (", + ccff_mem_model->prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, 0, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 76e7848ca..f6a159f22 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -851,7 +851,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, const t_spice_model* cur_spice_model, boolean dump_port_type, boolean recursive, - boolean require_explicit_port_map) { + boolean require_explicit_port_map, + boolean is_lib_name) { int dumped_port_cnt; boolean dump_comma = FALSE; t_spice_model_port* cur_spice_model_port = NULL; @@ -900,9 +901,13 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, } else { /* Add explicit port mapping if required */ if (TRUE == require_explicit_port_map ) { - fprintf(fp, ".%s(", - cur_spice_model_port->lib_name); - //cur_spice_model_port->prefix); + if (TRUE == is_lib_name) { + fprintf(fp, ".%s(", + cur_spice_model_port->lib_name); + } else { + fprintf(fp, ".%s(", + cur_spice_model_port->prefix); + } } fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix, @@ -1555,6 +1560,7 @@ void dump_verilog_sram_local_ports(FILE* fp, t_spice_model_port** blb_port = NULL; t_spice_model_port** wlb_port = NULL; t_spice_model* cur_sram_verilog_model = NULL; + t_spice_model* ccff_mem_model = NULL; /* Check the file handler*/ if (NULL == fp) { @@ -1572,6 +1578,10 @@ void dump_verilog_sram_local_ports(FILE* fp, __FILE__, __LINE__, sram_lsb, sram_msb); return; } + + /* Get model of the configuration chain */ + get_sram_orgz_info_mem_model(cur_sram_orgz_info, &ccff_mem_model); + switch (cur_sram_orgz_info->type) { case SPICE_SRAM_STANDALONE: case SPICE_SRAM_MEMORY_BANK: @@ -1588,7 +1598,8 @@ void dump_verilog_sram_local_ports(FILE* fp, case SPICE_SRAM_SCAN_CHAIN: /* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */ if (true == is_explicit_mapping) { - fprintf(fp, ".ccff_ccff_head("); + fprintf(fp, ".%s_ccff_head(", + ccff_mem_model->prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, sram_lsb, sram_lsb, @@ -1599,7 +1610,8 @@ void dump_verilog_sram_local_ports(FILE* fp, fprintf(fp, ",\n"); /* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */ if (true == is_explicit_mapping) { - fprintf(fp, ".ccff_ccff_tail("); + fprintf(fp, ".%s_ccff_tail(", + ccff_mem_model->prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, sram_msb, sram_msb, @@ -1859,7 +1871,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, @@ -1912,7 +1924,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/ @@ -1929,7 +1941,7 @@ void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_i fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ @@ -2025,7 +2037,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_num_sram); /* Input*/ @@ -2065,7 +2077,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_out[%d], ", cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Input*/ @@ -2082,7 +2094,7 @@ void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ (", cur_sram_verilog_model->name, cur_sram_verilog_model->prefix, cur_sram_verilog_model->cnt); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE, TRUE)) { fprintf(fp, ",\n"); } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ @@ -3061,7 +3073,7 @@ void dump_verilog_mem_module_port_map(FILE* fp, * Other ports are not accepted!!! */ /* 1. Global ports! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, mem_model, dump_port_type, TRUE, require_explicit_port_map)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, mem_model, dump_port_type, TRUE, require_explicit_port_map, TRUE)) { dump_first_comma = TRUE; } @@ -3178,7 +3190,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, } /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } @@ -3226,7 +3238,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, case SPICE_SRAM_STANDALONE: /* SRAM subckts*/ /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping), TRUE)) { fprintf(fp, ",\n"); } fprintf(fp, "%s_in[%d:%d], ", diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 2a39d5fff..ab5a98d2f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -74,7 +74,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, const t_spice_model* cur_spice_model, boolean dump_port_type, boolean recursive, - boolean require_explicit_port_map); + boolean require_explicit_port_map, + boolean is_lib_name); int dump_verilog_global_ports(FILE* fp, t_llist* head, boolean dump_port_type,