refactored RRAM MUX verilog generation
This commit is contained in:
tangxifan
parent
0711aa1bd6
commit
6a5b50facf
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@ -608,6 +608,14 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager,
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/* Make sure we have a valid file handler*/
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check_file_handler(fp);
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/* Get the input ports from the mux */
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std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
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/* Get the output ports from the mux */
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std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true);
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/* Get the BL and WL ports from the mux */
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std::vector<CircuitPortId> mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true);
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std::vector<CircuitPortId> mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true);
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/* Generate the Verilog netlist according to the mux_graph */
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/* Find out the number of inputs */
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size_t num_inputs = mux_graph.num_inputs();
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@ -621,6 +629,11 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager,
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VTR_ASSERT(1 == num_outputs);
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/* MUX graph must have only 1 level*/
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VTR_ASSERT(1 == mux_graph.num_levels());
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/* MUX graph must have only 1 input and 1 BLB and 1 WL port */
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VTR_ASSERT(1 == mux_input_ports.size());
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VTR_ASSERT(1 == mux_output_ports.size());
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VTR_ASSERT(1 == mux_blb_ports.size());
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VTR_ASSERT(1 == mux_wl_ports.size());
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId module_id = module_manager.add_module(module_name);
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@ -634,19 +647,23 @@ void generate_verilog_rram_mux_branch_module(ModuleManager& module_manager,
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BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
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module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT);
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}
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/* Add each input port */
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BasicPort input_port("in", num_inputs);
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BasicPort input_port(circuit_lib.port_lib_name(mux_input_ports[0]), num_inputs);
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module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT);
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/* Add each output port */
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BasicPort output_port("out", num_outputs);
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BasicPort output_port(circuit_lib.port_lib_name(mux_output_ports[0]), num_outputs);
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module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT);
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/* Add RRAM programming ports,
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* RRAM MUXes require one more pair of BLB and WL
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* to configure the memories. See schematic for details
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*/
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BasicPort blb_port("blb", num_mems + 1);
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BasicPort blb_port(circuit_lib.port_lib_name(mux_blb_ports[0]), num_mems + 1);
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module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT);
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BasicPort wl_port("wl", num_mems + 1);
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BasicPort wl_port(circuit_lib.port_lib_name(mux_wl_ports[0]), num_mems + 1);
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module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT);
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/* dump module definition + ports */
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@ -929,7 +946,6 @@ void generate_verilog_cmos_mux_module_tgate_multiplexing_structure(ModuleManager
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print_verilog_comment(fp, std::string("---- END Internal wires of a CMOS MUX module -----"));
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fp << std::endl;
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print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX module -----"));
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/* Iterate over all the internal nodes and output nodes in the mux graph */
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for (const auto& node : mux_graph.non_input_nodes()) {
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print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch CMOS MUX module -----"));
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@ -1414,6 +1430,391 @@ void generate_verilog_cmos_mux_module(ModuleManager& module_manager,
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print_verilog_module_end(fp, module_name);
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}
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/********************************************************************
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* Generate the 4T1R-based internal logic
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* (multiplexing structure) for a multiplexer in Verilog codes
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* This function will :
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* 1. build a multiplexing structure by instanciating the branch circuits
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* generated before
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* 2. add intermediate buffers between multiplexing stages if specified.
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*******************************************************************/
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static
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void generate_verilog_rram_mux_module_multiplexing_structure(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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std::fstream& fp,
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const ModuleId& module_id,
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const CircuitModelId& circuit_model,
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const MuxGraph& mux_graph) {
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/* Make sure we have a valid file handler*/
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check_file_handler(fp);
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/* Find the actual mux size */
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size_t mux_size = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs());
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/* Get the BL and WL ports from the mux */
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std::vector<CircuitPortId> mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true);
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std::vector<CircuitPortId> mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true);
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/* MUX graph must have only 1 BLB and 1 WL port */
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VTR_ASSERT(1 == mux_blb_ports.size());
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VTR_ASSERT(1 == mux_wl_ports.size());
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/* Build the location map of intermediate buffers */
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std::vector<bool> inter_buffer_location_map = build_mux_intermediate_buffer_location_map(circuit_lib, circuit_model, mux_graph.num_node_levels());
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print_verilog_comment(fp, std::string("---- BEGIN Internal Logic of a RRAM-based MUX module -----"));
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print_verilog_comment(fp, std::string("---- BEGIN Internal wires of a RRAM-based MUX module -----"));
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/* Print local wires which are the nodes in the mux graph */
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for (size_t level = 0; level < mux_graph.num_levels(); ++level) {
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/* Print the internal wires located at this level */
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BasicPort internal_wire_port(generate_verilog_mux_node_name(level, false), mux_graph.num_nodes_at_level(level));
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fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_port) << ";" << std::endl;
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/* Identify if an intermediate buffer is needed */
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if (false == inter_buffer_location_map[level]) {
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continue;
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}
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BasicPort internal_wire_buffered_port(generate_verilog_mux_node_name(level, true), mux_graph.num_nodes_at_level(level));
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fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, internal_wire_buffered_port) << std::endl;
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}
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print_verilog_comment(fp, std::string("---- END Internal wires of a RRAM-based MUX module -----"));
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fp << std::endl;
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/* Iterate over all the internal nodes and output nodes in the mux graph */
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for (const auto& node : mux_graph.non_input_nodes()) {
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print_verilog_comment(fp, std::string("---- BEGIN Instanciation of a branch RRAM-based MUX module -----"));
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/* Get the size of branch circuit
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* Instanciate an branch circuit by the size (fan-in) of the node
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*/
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size_t branch_size = mux_graph.node_in_edges(node).size();
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/* Get the node level and index in the current level */
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size_t output_node_level = mux_graph.node_level(node);
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size_t output_node_index_at_level = mux_graph.node_index_at_level(node);
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/* Get the nodes which drive the root_node */
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std::vector<MuxNodeId> input_nodes;
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for (const auto& edge : mux_graph.node_in_edges(node)) {
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/* Get the nodes drive the edge */
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for (const auto& src_node : mux_graph.edge_src_nodes(edge)) {
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input_nodes.push_back(src_node);
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}
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}
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/* Number of inputs should match the branch_input_size!!! */
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VTR_ASSERT(input_nodes.size() == branch_size);
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/* Get the mems in the branch circuits */
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std::vector<MuxMemId> mems;
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for (const auto& edge : mux_graph.node_in_edges(node)) {
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/* Get the mem control the edge */
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MuxMemId mem = mux_graph.find_edge_mem(edge);
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/* Add the mem if it is not in the list */
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if (mems.end() == std::find(mems.begin(), mems.end(), mem)) {
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mems.push_back(mem);
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}
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}
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/* Instanciate the branch module which is a tgate-based module
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*/
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std::string branch_module_name= generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, branch_size, verilog_mux_basis_posfix);
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/* Get the moduleId for the submodule */
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ModuleId branch_module_id = module_manager.find_module(branch_module_name);
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/* We must have one */
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VTR_ASSERT(ModuleId::INVALID() != branch_module_id);
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/* Create a port-to-port map */
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std::map<std::string, BasicPort> port2port_name_map;
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/* TODO: the branch module name should NOT be hard-coded. Use the port lib_name given by users! */
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/* All the input node names organized in bus */
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std::vector<BasicPort> branch_node_input_ports;
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for (const auto& input_node : input_nodes) {
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/* Generate the port info of each input node */
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size_t input_node_level = mux_graph.node_level(input_node);
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size_t input_node_index_at_level = mux_graph.node_index_at_level(input_node);
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BasicPort branch_node_input_port(generate_verilog_mux_node_name(input_node_level, inter_buffer_location_map[input_node_level]), input_node_index_at_level, input_node_index_at_level);
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branch_node_input_ports.push_back(branch_node_input_port);
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}
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/* Create the port info for the input */
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/* TODO: the naming could be more flexible? */
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BasicPort instance_input_port = generate_verilog_bus_port(branch_node_input_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_in"));
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/* If we have more than 1 port in the combined instance ports ,
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* output a local wire */
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if (1 < combine_verilog_ports(branch_node_input_ports).size()) {
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/* Print a local wire for the merged ports */
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fp << "\t" << generate_verilog_local_wire(instance_input_port, branch_node_input_ports) << std::endl;
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} else {
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/* Safety check */
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VTR_ASSERT(1 == combine_verilog_ports(branch_node_input_ports).size());
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}
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/* Link nodes to input ports for the branch module */
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ModulePortId module_input_port_id = module_manager.find_module_port(branch_module_id, "in");
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VTR_ASSERT(ModulePortId::INVALID() != module_input_port_id);
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/* Get the port from module */
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BasicPort module_input_port = module_manager.module_port(branch_module_id, module_input_port_id);
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port2port_name_map[module_input_port.get_name()] = instance_input_port;
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/* Link nodes to output ports for the branch module */
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BasicPort instance_output_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level);
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ModulePortId module_output_port_id = module_manager.find_module_port(branch_module_id, "out");
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VTR_ASSERT(ModulePortId::INVALID() != module_output_port_id);
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/* Get the port from module */
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BasicPort module_output_port = module_manager.module_port(branch_module_id, module_output_port_id);
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port2port_name_map[module_output_port.get_name()] = instance_output_port;
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/* All the mem node names organized in bus
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* RRAM-based MUX uses BLB and WL to control memories
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*/
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std::vector<BasicPort> branch_node_blb_ports;
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for (const auto& mem : mems) {
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/* Generate the port info of each mem node:
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*/
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BasicPort branch_node_blb_port(circuit_lib.port_lib_name(mux_blb_ports[0]), size_t(mem), size_t(mem));
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branch_node_blb_ports.push_back(branch_node_blb_port);
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}
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/* Every stage, we have an additonal BLB and WL in controlling purpose
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* The additional BLB is arranged at the tail of BLB port
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* For example:
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* The total port width is BLB[0 ... <num_mem> + <num_levels> - 1]
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* The regular BLB used by branches are BLB[0 .. <num_mem> - 1]
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* The additional BLB used by branches are BLB[<num_mem> .. <num_mem> + <num_levels> - 1]
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*
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* output_node_level is always larger than the mem_level by 1
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*/
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branch_node_blb_ports.push_back(BasicPort(circuit_lib.port_lib_name(mux_blb_ports[0]),
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mux_graph.num_memory_bits() + output_node_level - 1,
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mux_graph.num_memory_bits() + output_node_level - 1)
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);
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/* Create the port info for the input */
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/* TODO: the naming could be more flexible? */
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BasicPort instance_blb_port = generate_verilog_bus_port(branch_node_blb_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_blb"));
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/* If we have more than 1 port in the combined instance ports ,
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* output a local wire */
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if (1 < combine_verilog_ports(branch_node_blb_ports).size()) {
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/* Print a local wire for the merged ports */
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fp << "\t" << generate_verilog_local_wire(instance_blb_port, branch_node_blb_ports) << std::endl;
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} else {
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/* Safety check */
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VTR_ASSERT(1 == combine_verilog_ports(branch_node_blb_ports).size());
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}
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/* Link nodes to BLB ports for the branch module */
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ModulePortId module_blb_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_lib_name(mux_blb_ports[0]));
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VTR_ASSERT(ModulePortId::INVALID() != module_blb_port_id);
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/* Get the port from module */
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BasicPort module_blb_port = module_manager.module_port(branch_module_id, module_blb_port_id);
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port2port_name_map[module_blb_port.get_name()] = instance_blb_port;
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std::vector<BasicPort> branch_node_wl_ports;
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for (const auto& mem : mems) {
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/* Generate the port info of each mem node:
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*/
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BasicPort branch_node_blb_port(circuit_lib.port_lib_name(mux_wl_ports[0]), size_t(mem), size_t(mem));
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branch_node_wl_ports.push_back(branch_node_blb_port);
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}
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/* Every stage, we have an additonal BLB and WL in controlling purpose
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* The additional BLB is arranged at the tail of BLB port
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* For example:
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* The total port width is WL[0 ... <num_mem> + <num_levels> - 1]
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* The regular BLB used by branches are WL[0 .. <num_mem> - 1]
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* The additional BLB used by branches are WL[<num_mem> .. <num_mem> + <num_levels> - 1]
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*
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* output_node_level is always larger than the mem_level by 1
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*/
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branch_node_wl_ports.push_back(BasicPort(circuit_lib.port_lib_name(mux_wl_ports[0]),
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mux_graph.num_memory_bits() + output_node_level - 1,
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mux_graph.num_memory_bits() + output_node_level - 1)
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);
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/* Create the port info for the WL */
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/* TODO: the naming could be more flexible? */
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BasicPort instance_wl_port = generate_verilog_bus_port(branch_node_wl_ports, std::string(generate_verilog_mux_node_name(output_node_level, false) + "_wl"));
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/* If we have more than 1 port in the combined instance ports ,
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* output a local wire */
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if (1 < combine_verilog_ports(branch_node_wl_ports).size()) {
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/* Print a local wire for the merged ports */
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fp << "\t" << generate_verilog_local_wire(instance_wl_port, branch_node_wl_ports) << std::endl;
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} else {
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/* Safety check */
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VTR_ASSERT(1 == combine_verilog_ports(branch_node_wl_ports).size());
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}
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/* Link nodes to BLB ports for the branch module */
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ModulePortId module_wl_port_id = module_manager.find_module_port(branch_module_id, circuit_lib.port_lib_name(mux_wl_ports[0]));
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VTR_ASSERT(ModulePortId::INVALID() != module_wl_port_id);
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/* Get the port from module */
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BasicPort module_wl_port = module_manager.module_port(branch_module_id, module_wl_port_id);
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port2port_name_map[module_wl_port.get_name()] = instance_wl_port;
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/* Output an instance of the module */
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print_verilog_module_instance(fp, module_manager, module_id, branch_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model));
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/* IMPORTANT: this update MUST be called after the instance outputting!!!!
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* update the module manager with the relationship between the parent and child modules
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*/
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module_manager.add_child_module(module_id, branch_module_id);
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print_verilog_comment(fp, std::string("---- END Instanciation of a branch RRAM-based MUX module -----"));
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fp << std::endl;
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if (false == inter_buffer_location_map[output_node_level]) {
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continue; /* No need for intermediate buffers */
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}
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print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an intermediate buffer modules -----"));
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/* Now we need to add intermediate buffers by instanciating the modules */
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CircuitModelId buffer_model = circuit_lib.lut_intermediate_buffer_model(circuit_model);
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/* We must have a valid model id */
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VTR_ASSERT(CircuitModelId::INVALID() != buffer_model);
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BasicPort buffer_instance_input_port(generate_verilog_mux_node_name(output_node_level, false), output_node_index_at_level, output_node_index_at_level);
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BasicPort buffer_instance_output_port(generate_verilog_mux_node_name(output_node_level, true), output_node_index_at_level, output_node_index_at_level);
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print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, buffer_model, buffer_instance_input_port, buffer_instance_output_port);
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print_verilog_comment(fp, std::string("---- END Instanciation of an intermediate buffer module -----"));
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fp << std::endl;
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}
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print_verilog_comment(fp, std::string("---- END Internal Logic of a RRAM-based MUX module -----"));
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fp << std::endl;
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}
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/*********************************************************************
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* Generate Verilog codes modeling a RRAM-based multiplexer with the given size
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* The Verilog module will consist of three parts:
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* 1. instances of the branch circuits of multiplexers which are generated before
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* This builds up the 4T1R-based multiplexing structure
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*
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* BLB WL
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* | | ...
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* v v
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* +--------+
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* in[0]-->| | BLB WL
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* ...| Branch |-----+ | |
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* in -->| 0 | | v v
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* [N-1] +--------+ | +--------+
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* ... -->| |
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* BLBs WLs ...| Branch |
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* | | ... -->| X |
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* v v +--------+
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* +--------+ |
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* -->| | |
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* ...| Branch |----+
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* -->| i |
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* +--------+
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*
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* 2. Input buffers/inverters
|
||||
* 3. Output buffers/inverters
|
||||
*********************************************************************/
|
||||
static
|
||||
void generate_verilog_rram_mux_module(ModuleManager& module_manager,
|
||||
const CircuitLibrary& circuit_lib,
|
||||
std::fstream& fp,
|
||||
const CircuitModelId& circuit_model,
|
||||
const std::string& module_name,
|
||||
const MuxGraph& mux_graph) {
|
||||
/* Error out for the conditions where we are not yet supported! */
|
||||
if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
|
||||
/* RRAM LUT is not supported now... */
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
"(File:%s,[LINE%d])RRAM-based LUT is not supported (Circuit model: %s)!\n",
|
||||
__FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str());
|
||||
exit(1);
|
||||
}
|
||||
|
||||
/* Get the global ports required by MUX (and any submodules) */
|
||||
std::vector<CircuitPortId> mux_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
|
||||
/* Get the input ports from the mux */
|
||||
std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
|
||||
/* Get the output ports from the mux */
|
||||
std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true);
|
||||
/* Get the BL and WL ports from the mux */
|
||||
std::vector<CircuitPortId> mux_blb_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_BLB, true);
|
||||
std::vector<CircuitPortId> mux_wl_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_WL, true);
|
||||
|
||||
/* Make sure we have a valid file handler*/
|
||||
check_file_handler(fp);
|
||||
|
||||
/* Generate the Verilog netlist according to the mux_graph */
|
||||
/* Find out the number of data-path inputs */
|
||||
size_t num_inputs = find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs());
|
||||
/* Find out the number of outputs */
|
||||
size_t num_outputs = mux_graph.num_outputs();
|
||||
/* Find out the number of memory bits */
|
||||
size_t num_mems = mux_graph.num_memory_bits();
|
||||
|
||||
/* Check codes to ensure the port of Verilog netlists will match */
|
||||
/* MUX graph must have only 1 input and 1 BLB and 1 WL port */
|
||||
VTR_ASSERT(1 == mux_input_ports.size());
|
||||
VTR_ASSERT(1 == mux_blb_ports.size());
|
||||
VTR_ASSERT(1 == mux_wl_ports.size());
|
||||
|
||||
/* Create a Verilog Module based on the circuit model, and add to module manager */
|
||||
ModuleId module_id = module_manager.add_module(module_name);
|
||||
VTR_ASSERT(ModuleId::INVALID() != module_id);
|
||||
/* Add module ports */
|
||||
/* Add each global port */
|
||||
for (const auto& port : mux_global_ports) {
|
||||
/* Configure each global port */
|
||||
BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
|
||||
module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT);
|
||||
}
|
||||
/* Add each input port */
|
||||
size_t input_port_cnt = 0;
|
||||
for (const auto& port : mux_input_ports) {
|
||||
BasicPort input_port(circuit_lib.port_lib_name(port), num_inputs);
|
||||
module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT);
|
||||
/* Update counter */
|
||||
input_port_cnt++;
|
||||
}
|
||||
/* Double check: We should have only 1 input port generated here! */
|
||||
VTR_ASSERT(1 == input_port_cnt);
|
||||
|
||||
for (const auto& port : mux_output_ports) {
|
||||
BasicPort output_port(circuit_lib.port_lib_name(port), num_outputs);
|
||||
if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
|
||||
output_port.set_width(circuit_lib.port_size(port));
|
||||
}
|
||||
module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT);
|
||||
}
|
||||
|
||||
/* BLB port */
|
||||
for (const auto& port : mux_blb_ports) {
|
||||
/* IMPORTANT: RRAM-based MUX has an additional BLB pin per level
|
||||
* So, the actual port width of BLB should be added by the number of levels of the MUX graph
|
||||
*/
|
||||
BasicPort blb_port(circuit_lib.port_lib_name(port), num_mems + mux_graph.num_levels());
|
||||
module_manager.add_port(module_id, blb_port, ModuleManager::MODULE_INPUT_PORT);
|
||||
}
|
||||
|
||||
/* WL port */
|
||||
for (const auto& port : mux_wl_ports) {
|
||||
/* IMPORTANT: RRAM-based MUX has an additional WL pin per level
|
||||
* So, the actual port width of WL should be added by the number of levels of the MUX graph
|
||||
*/
|
||||
BasicPort wl_port(circuit_lib.port_lib_name(port), num_mems + mux_graph.num_levels());
|
||||
module_manager.add_port(module_id, wl_port, ModuleManager::MODULE_INPUT_PORT);
|
||||
}
|
||||
|
||||
/* dump module definition + ports */
|
||||
print_verilog_module_declaration(fp, module_manager, module_id);
|
||||
|
||||
/* TODO: Print the internal logic in Verilog codes */
|
||||
generate_verilog_rram_mux_module_multiplexing_structure(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph);
|
||||
|
||||
/* Print the input and output buffers in Verilog codes */
|
||||
/* TODO, we should rename the follow functions to a generic name? Since they are applicable to both MUXes */
|
||||
generate_verilog_cmos_mux_module_input_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph);
|
||||
generate_verilog_cmos_mux_module_output_buffers(module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph);
|
||||
|
||||
/* Put an end to the Verilog module */
|
||||
print_verilog_module_end(fp, module_name);
|
||||
}
|
||||
|
||||
|
||||
/***********************************************
|
||||
* Generate Verilog codes modeling a multiplexer
|
||||
* with the given graph-level description
|
||||
|
|
@ -1436,10 +1837,7 @@ void generate_verilog_mux_module(ModuleManager& module_manager,
|
|||
break;
|
||||
case SPICE_MODEL_DESIGN_RRAM:
|
||||
/* TODO: RRAM-based Multiplexer Verilog module generation */
|
||||
/*
|
||||
generate_verilog_rram_mux_branch_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph,
|
||||
circuit_lib.dump_structural_verilog(circuit_model));
|
||||
*/
|
||||
generate_verilog_rram_mux_module(module_manager, circuit_lib, fp, circuit_model, module_name, mux_graph);
|
||||
break;
|
||||
default:
|
||||
vpr_printf(TIO_MESSAGE_ERROR,
|
||||
|
|
|
|||
Loading…
Reference in New Issue