From 9e911cd288e67553f1ef6b15b0fd7f1348dc0463 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 14 Jan 2020 15:04:47 -0700 Subject: [PATCH 1/2] bug fixing for direct connection when pin duplication is applied --- .../build_grid_module_duplicated_pins.cpp | 39 +++++++++++++++++-- .../build_top_module_connection.cpp | 13 ++++++- 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp index 7fa00dcab..4b747f77f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp @@ -80,9 +80,12 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, /* Reach here, it means this pin is on this side */ int class_id = grid_type_descriptor->pin_class[ipin]; e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type; - /* Generate the pin name */ - if (RECEIVER == pin_class_type) { - /* For each RECEIVER PIN, we do not duplicate */ + /* Generate the pin name + * For each RECEIVER PIN or DRIVER PIN for direct connection, + * we do not duplicate in these cases */ + if ( (RECEIVER == pin_class_type) + /* Xifan: I assume that each direct connection pin must have Fc=0. */ + || ( (DRIVER == pin_class_type) && (0. == grid_type_descriptor->Fc[ipin]) ) ) { vtr::Point dummy_coordinate; std::string port_name = generate_grid_port_name(dummy_coordinate, iheight, side, ipin, false); BasicPort grid_port(port_name, 0, 0); @@ -155,6 +158,36 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m if (1 != grid_type_descriptor->pinloc[pin_height][side][grid_pin_index]) { continue; } + + /* Pins for direct connection are NOT duplicated. + * Follow the traditional recipe when adding nets! + * Xifan: I assume that each direct connection pin must have Fc=0. + */ + if (0. == grid_type_descriptor->Fc[grid_pin_index]) { + /* Create a net to connect the grid pin to child module pin */ + ModuleNetId net = module_manager.create_module_net(grid_module); + /* Find the port in grid_module */ + vtr::Point dummy_coordinate; + std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_height, side, grid_pin_index, false); + ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id)); + + /* Grid port always has only 1 pin, it is assumed when adding these ports to the module + * if you need a change, please also change the port adding codes + */ + size_t grid_module_pin_id = 0; + /* Find the port in child module */ + std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port); + ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id)); + size_t child_module_pin_id = pb_graph_pin->pin_number; + /* Add net sources and sinks: + * For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin + */ + module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id); + module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id); + continue; + } /* Reach here, it means this pin is on this side */ /* Create a net to connect the grid pin to child module pin */ ModuleNetId net = module_manager.create_module_net(grid_module); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.cpp index 07eadf77d..5c5af2627 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_connection.cpp @@ -215,7 +215,18 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()]; size_t src_grid_pin_index = rr_gsb.get_opin_node(side_manager.get_side(), inode)->ptc_num; size_t src_grid_pin_height = find_grid_pin_height(grids, grid_coordinate, src_grid_pin_index); - std::string src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, sb_side2postfix_map[side_manager.get_side()]); + + /* Pins for direct connection are NOT duplicated. + * Follow the traditional recipe when adding nets! + * Xifan: I assume that each direct connection pin must have Fc=0. + * For other duplicated pins, we follow the new naming + */ + std::string src_grid_port_name; + if (0. == grids[grid_coordinate.x()][grid_coordinate.y()].type->Fc[src_grid_pin_index]) { + src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, false); + } else { + src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_height, rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), src_grid_pin_index, sb_side2postfix_map[side_manager.get_side()]); + } ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id)); BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id); From 622ba9bb8c0e679628c558d66c0329245a49cec9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 17 Jan 2020 11:24:33 -0700 Subject: [PATCH 2/2] bug fixed in SDC for CBs and SBs: remove useless module names --- .../pnr_sdc_routing_writer.cpp | 20 ++++++------- .../backend_assistant/sdc_writer_utils.cpp | 29 +++++++++++++++++-- .../backend_assistant/sdc_writer_utils.h | 8 +++++ 3 files changed, 45 insertions(+), 12 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp index ac7fbd3d1..6e1a1f89d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp @@ -82,11 +82,11 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp, /* Find the starting points */ for (const ModulePortId& module_input_port : module_input_ports) { /* Constrain a path */ - print_pnr_sdc_constrain_module_port2port_timing(fp, - module_manager, - sb_module, module_input_port, - sb_module, module_output_port, - switch_delays[module_input_port]); + print_pnr_sdc_constrain_port2port_timing(fp, + module_manager, + sb_module, module_input_port, + sb_module, module_output_port, + switch_delays[module_input_port]); } } @@ -271,11 +271,11 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp, /* Find the starting points */ for (const ModulePortId& module_input_port : module_input_ports) { /* Constrain a path */ - print_pnr_sdc_constrain_module_port2port_timing(fp, - module_manager, - cb_module, module_input_port, - cb_module, module_output_port, - switch_delays[module_input_port]); + print_pnr_sdc_constrain_port2port_timing(fp, + module_manager, + cb_module, module_input_port, + cb_module, module_output_port, + switch_delays[module_input_port]); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp index 0613cac7a..b3228d007 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp @@ -67,12 +67,16 @@ void print_pnr_sdc_constrain_max_delay(std::fstream& fp, fp << "set_max_delay"; fp << " -from "; - fp << src_instance_name << "/"; + if (!src_instance_name.empty()) { + fp << src_instance_name << "/"; + } fp << src_port_name; fp << " -to "; - fp << des_instance_name << "/"; + if (!des_instance_name.empty()) { + fp << des_instance_name << "/"; + } fp << des_port_name; fp << " " << std::setprecision(10) << delay; @@ -100,6 +104,27 @@ void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, } +/******************************************************************** + * Constrain a path between two ports of a module with a given timing value + * This function will NOT output the module name + * Note: this function uses set_max_delay !!! + *******************************************************************/ +void print_pnr_sdc_constrain_port2port_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& input_parent_module_id, + const ModulePortId& module_input_port_id, + const ModuleId& output_parent_module_id, + const ModulePortId& module_output_port_id, + const float& tmax) { + print_pnr_sdc_constrain_max_delay(fp, + std::string(), + generate_sdc_port(module_manager.module_port(input_parent_module_id, module_input_port_id)), + std::string(), + generate_sdc_port(module_manager.module_port(output_parent_module_id, module_output_port_id)), + tmax); + +} + /******************************************************************** * Disable timing for a port *******************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h index 9483f0379..d5296032d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h @@ -26,6 +26,14 @@ void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp, const ModulePortId& module_output_port_id, const float& tmax); +void print_pnr_sdc_constrain_port2port_timing(std::fstream& fp, + const ModuleManager& module_manager, + const ModuleId& input_parent_module_id, + const ModulePortId& module_input_port_id, + const ModuleId& output_parent_module_id, + const ModulePortId& module_output_port_id, + const float& tmax); + void print_sdc_disable_port_timing(std::fstream& fp, const BasicPort& port);