diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml index c4642ed55..ab5e95413 100644 --- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml @@ -397,7 +397,7 @@ - + diff --git a/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml b/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml index fb5192145..426bcdcf6 100755 --- a/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml +++ b/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml @@ -273,7 +273,7 @@ - + @@ -300,7 +300,7 @@ - + @@ -515,7 +515,7 @@ - + @@ -632,16 +632,16 @@ - - - + + + - + @@ -650,7 +650,7 @@ - + @@ -660,7 +660,7 @@ - + @@ -696,12 +696,12 @@ - - - + + + - + @@ -732,7 +732,7 @@ - + @@ -750,13 +750,13 @@ - + - + @@ -769,7 +769,7 @@ - + @@ -795,9 +795,9 @@ - - - + + + @@ -805,7 +805,7 @@ - + @@ -815,7 +815,7 @@ - + @@ -833,7 +833,7 @@ - + input ports */ dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, subckt_require_explicit_port_map); + /* my_bool_to_boolean(is_explicit_mapping));*/ /* IOPADs requires a specical port to output */ if (SPICE_MODEL_IOPAD == verilog_model->type) { fprintf(fp, ",\n"); assert(1 == num_pad_port); assert(NULL != pad_ports[0]); /* Add explicit port mapping if required */ - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { + /*if (true == is_explicit_mapping) {*/ fprintf(fp, ".%s (", pad_ports[0]->lib_name); } /* Print inout port */ fprintf(fp, "%s%s[%d]", gio_inout_prefix, verilog_model->prefix, verilog_model->cnt); - if (TRUE == subckt_require_explicit_port_map) { + if (TRUE == subckt_require_explicit_port_map) { + /*if (true == is_explicit_mapping) {*/ fprintf(fp, ")"); } fprintf(fp, ", "); @@ -300,7 +304,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 1, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map || is_explicit_mapping)) { + && (TRUE == subckt_require_explicit_port_map)) { fprintf(fp, ")"); } break; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c index 87487220c..656d0b26d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c @@ -2740,6 +2740,9 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts, vpr_printf(TIO_MESSAGE_INFO, "Generating TCL script to report timing for routing wires\n"); + vpr_printf(TIO_MESSAGE_INFO, + "Generating TCL script to report timing for routing wires horizontal\n"); + /* Start with horizontal SBs*/ /* We start from a SB[x][y] */ DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range(); for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { @@ -2759,6 +2762,9 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts, if (1 == rr_sb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes) { continue; } + if (CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) { + continue; + } /* Check if L_wire exists in the linked list */ L_wire = get_rr_node_wire_length(rr_sb.get_chan_node(side_manager.get_side(), itrack)); /* Get counter */ @@ -2793,6 +2799,72 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts, } } + /* close file*/ + fclose_wire_L_file_handler_in_llist(rr_path_cnt); + /* Need to reset the different variables */ + rr_path_cnt = NULL; + wireL_cnt = NULL; + path_cnt = 0; + + vpr_printf(TIO_MESSAGE_INFO, + "Generating TCL script to report timing for routing wires vertical\n"); + /* Continue with vertical SBs*/ + /* We start from a SB[x][y] */ + for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { + const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy); + for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) { + Side side_manager(side); + for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { + assert((CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) + ||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)); + /* We only care the output port and it should indicate a SB mux */ + if ( (OUT_PORT != rr_sb.get_chan_node_direction(side_manager.get_side(), itrack)) + || (false != rr_sb.is_sb_node_passing_wire(side_manager.get_side(), itrack))) { + continue; + } + /* Bypass if we have only 1 driving node */ + if (1 == rr_sb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes) { + continue; + } + if (CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) { + continue; + } + /* Check if L_wire exists in the linked list */ + L_wire = get_rr_node_wire_length(rr_sb.get_chan_node(side_manager.get_side(), itrack)); + /* Get counter */ + rr_path_cnt = get_wire_L_counter_in_llist(rr_path_cnt, trpt_opts, "vertical", L_wire, &wireL_cnt); + path_cnt = wireL_cnt->cnt; + fp = wireL_cnt->file_handler; + /* This is a new L-wire, create the file handler and the mkdir command to the TCL script */ + if (0 == path_cnt) { + fprintf(fp, "exec mkdir -p %s\n", + gen_verilog_one_routing_report_timing_Lwire_dir_path(fpga_verilog_opts.report_timing_path, L_wire)); + } + /* Restore the disable_timing for the SB outputs on the path */ + /*fprintf(fp, "# Restore disable timing for the following Switch Block output:\n"); + restore_disable_timing_one_sb_output(fp, + rr_sb, + rr_sb.get_chan_node(side_manager.get_side(), itrack));*/ + fprintf(fp, "# Report timing for all the paths using this output:\n"); + /* Dump report_timing command */ + verilog_generate_one_routing_segmental_report_timing(fp, fpga_verilog_opts, + rr_sb, + side_manager.get_side(), itrack, + LL_rr_node, "vertical", &path_cnt); + /* Disable the timing again */ + /*fprintf(fp, "# Set disable timing for the following Switch Block output:\n"); + set_disable_timing_one_sb_output(fp, + rr_sb, + rr_sb.get_chan_node(side_manager.get_side(), itrack));*/ + /* Update the wire L*/ + update_wire_L_counter_in_llist(rr_path_cnt, L_wire, path_cnt); + } + } + } + } + + /* close file*/ fclose_wire_L_file_handler_in_llist(rr_path_cnt); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 9d3431585..f23d437fd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -981,6 +981,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, int cur_bl, cur_wl; t_spice_model* mem_model = NULL; char* mem_subckt_name = NULL; + int num_input_port, num_output_port, num_sram_port; /* Check the file handler*/ if (NULL == fp) { @@ -1096,8 +1097,11 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ",\n"); } + t_spice_model_port** input_port = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + t_spice_model_port** output_port = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); if (TRUE == is_explicit_mapping) { - fprintf(fp, ".in("); + fprintf(fp, ".%s(", + input_port[0]->prefix); fprintf(fp, "%s_size%d_%d_inbus), ", verilog_model->prefix, mux_size, verilog_model->cnt); } @@ -1107,7 +1111,8 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, } /* Output port */ if (TRUE == is_explicit_mapping) { - fprintf(fp, ".out("); + fprintf(fp, ".%s(", + output_port[0]->prefix); dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT); fprintf(fp, ")"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index 345c89954..b70163422 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -2732,12 +2732,13 @@ void verilog_generate_sdc_pnr(t_sram_orgz_info* cur_sram_orgz_info, } /* Part 5. Output routing constraints for Connection Blocks */ - if (TRUE == sdc_opts.constrain_routing_channels) { + /* BC: Might not be useful as it constrains nets which are assigned too*/ + /*if (TRUE == sdc_opts.constrain_routing_channels) { verilog_generate_sdc_constrain_routing_channels(sdc_opts, arch, LL_nx, LL_ny, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data); - } + }*/ /* Part 6. Output routing constraints for Programmable blocks */ if (TRUE == sdc_opts.constrain_pbs) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index e0f09aebd..79a794729 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -722,8 +722,10 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp, t_spice_model* tgate_spice_model = cur_spice_model->pass_gate_logic->spice_model; int num_input_port = 0; int num_output_port = 0; + int num_sram_port = 0; t_spice_model_port** input_port = NULL; t_spice_model_port** output_port = NULL; + t_spice_model_port** sram_port = NULL; assert(TRUE == cur_spice_model->dump_structural_verilog); @@ -737,6 +739,7 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp, assert ( NULL != tgate_spice_model); input_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); output_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); + sram_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); /* Check */ assert ((3 == num_input_port)); @@ -764,9 +767,9 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp, fprintf(fp, "input [0:%d] in,\n", num_input_basis_subckt - 1); fprintf(fp, "output out,\n"); fprintf(fp, "input [0:%d] mem,\n", - num_mem - 1); + num_mem - 1/*, sram_port[0]->prefix*/); fprintf(fp, "input [0:%d] mem_inv);\n", - num_mem - 1); + num_mem - 1/*, sram_port[0]->prefix*/); /* Verilog Behavior description for a MUX */ fprintf(fp, "//---- Structure-level description -----\n"); /* Special case: only one memory, switch case is simpler @@ -1678,7 +1681,8 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, switch (cur_mux_structure) { case SPICE_MODEL_STRUCTURE_TREE: dump_verilog_cmos_mux_tree_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port, is_explicit_mapping); + spice_model, spice_mux_arch, + num_sram_port, sram_port, is_explicit_mapping); break; case SPICE_MODEL_STRUCTURE_ONELEVEL: dump_verilog_cmos_mux_onelevel_structure(fp, mux_basis_subckt_name, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index ca01c0f3b..67a31e10f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -902,8 +902,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, /* Add explicit port mapping if required */ if (TRUE == require_explicit_port_map ) { fprintf(fp, ".%s(", - cur_spice_model_port->lib_name); - /*cur_spice_model_port->prefix);*/ + cur_spice_model_port->lib_name); + //cur_spice_model_port->prefix); } fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix, @@ -2575,6 +2575,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m int num_mux_reserved_conf_bits, int num_mux_conf_bits, bool is_explicit_mapping) { + int num_sram_port; + t_spice_model_port** sram_port = find_spice_model_ports(mux_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE); /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -2595,7 +2597,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m * We do not need a prefix implying MUX name, size and index */ if (true == is_explicit_mapping) { - fprintf(fp, ".sram ("); + fprintf(fp, ".%s (", + sram_port[0]->prefix); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, @@ -2607,7 +2610,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m } fprintf(fp, ", "); if (TRUE == is_explicit_mapping) { - fprintf(fp, ".sram_inv ("); + fprintf(fp, ".%s_inv (", + sram_port[0]->prefix); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, @@ -2624,7 +2628,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m * We need a prefix implying MUX name, size and index */ if (TRUE == is_explicit_mapping) { - fprintf(fp, ".sram("); + fprintf(fp, ".%s (", + sram_port[0]->prefix); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, @@ -2636,7 +2641,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m } fprintf(fp, ",\n"); if (TRUE == is_explicit_mapping) { - fprintf(fp, ".sram_inv("); + fprintf(fp, ".%s_inv (", + sram_port[0]->prefix); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, @@ -3102,6 +3108,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, int num_bl_per_sram = 0; int num_wl_per_sram = 0; int iport = 0; + t_llist* spice_model_head = NULL; /* Check the file handler*/ if (NULL == fp) { @@ -3198,7 +3205,11 @@ void dump_verilog_mem_sram_submodule(FILE* fp, break; case SPICE_SRAM_SCAN_CHAIN: /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { + rec_stats_spice_model_global_ports(cur_sram_verilog_model, + TRUE, + &spice_model_head); + if (0 < dump_verilog_global_ports( fp, spice_model_head, FALSE, is_explicit_mapping)) { + //if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { fprintf(fp, ",\n"); } if (SPICE_MODEL_MUX == cur_verilog_model->type) { diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index 190ae5523..644c9c3f3 100755 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -25,7 +25,7 @@ arch_ff_keyword="FFPATHKEYWORD" # Remove previous designs rm -rf $verilog_output_dirpath/$verilog_output_dirname -mkdir ${OpenFPGA_path}/fpga_flow/arch/generated +mkdir -p ${OpenFPGA_path}/fpga_flow/arch/generated cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file @@ -33,7 +33,8 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd - # Run VPR -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping +#echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping" +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path