From 681e80d4b62c68c56494439c424fa4f4887ea007 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Sep 2020 10:39:22 -0600 Subject: [PATCH] [Regression tests] update frac_lut test case using more representative benchmarks --- .../fpga_verilog/lut_design/frac_lut/config/task.conf | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf index fbe91030d..1809feae5 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf @@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml # bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif # Modelsim is ok with this but icarus fails due to poor support on timing and looping #bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif @@ -39,9 +40,9 @@ bench1_top = routing_test bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v -bench2_top = and2_latch -bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act -bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v +bench2_top = and2_or2 +bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act +bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=