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[Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes

This commit is contained in:
tangxifan 2021-06-24 17:27:32 -06:00
parent 549657e1fb
commit 67dec810eb
3 changed files with 14 additions and 26 deletions
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6
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -206,12 +206,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
/* Print the title */ /* Print the title */
print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features"));
/* To enable functional verfication with Icarus */
if (true == verilog_testbench_opts.support_icarus_simulator()) {
print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1);
fp << std::endl;
}
/* To enable auto-checked simulation */ /* To enable auto-checked simulation */
if ( (true == verilog_testbench_opts.print_preconfig_top_testbench()) if ( (true == verilog_testbench_opts.print_preconfig_top_testbench())
|| (true == verilog_testbench_opts.print_top_testbench()) ) { || (true == verilog_testbench_opts.print_top_testbench()) ) {

4
openfpga/src/fpga_verilog/verilog_constants.h
View File

@ -13,10 +13,6 @@ constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to ena
constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms"; constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
// Icarus variables and flag
constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
// End of Icarus variables and flag
constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v"; constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v";
constexpr char* TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v"; constexpr char* TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
constexpr char* VERILOG_TOP_POSTFIX = "_top.v"; constexpr char* VERILOG_TOP_POSTFIX = "_top.v";

18
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -364,7 +364,8 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
const ModuleId &top_module, const ModuleId &top_module,
const CircuitLibrary& circuit_lib, const CircuitLibrary& circuit_lib,
const CircuitModelId& mem_model, const CircuitModelId& mem_model,
const BitstreamManager &bitstream_manager) { const BitstreamManager &bitstream_manager,
const bool& support_icarus_simulator) {
/* Skip the datab port if there is only 1 output port in memory model /* Skip the datab port if there is only 1 output port in memory model
* Currently, it assumes that the data output port is always defined while datab is optional * Currently, it assumes that the data output port is always defined while datab is optional
@ -379,21 +380,17 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----"));
print_verilog_preprocessing_flag(fp, std::string(ICARUS_SIMULATOR_FLAG));
/* Use assign syntax for Icarus simulator */ /* Use assign syntax for Icarus simulator */
if (support_icarus_simulator) {
print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module, print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module,
bitstream_manager, bitstream_manager,
output_datab_bits); output_datab_bits);
} else {
fp << "`else" << std::endl; /* Use deposit syntax for other simulators */
/* Use assign syntax for Icarus simulator */
print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module, print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module,
bitstream_manager, bitstream_manager,
output_datab_bits); output_datab_bits);
}
print_verilog_endif(fp);
print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----")); print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----"));
} }
@ -505,7 +502,8 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
/* Assign FPGA internal SRAM/Memory ports to bitstream values */ /* Assign FPGA internal SRAM/Memory ports to bitstream values */
print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module, print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module,
circuit_lib, sram_model, circuit_lib, sram_model,
bitstream_manager); bitstream_manager,
options.support_icarus_simulator());
/* Add signal initialization: /* Add signal initialization:
* Bypass writing codes to files due to the autogenerated codes are very large. * Bypass writing codes to files due to the autogenerated codes are very large.