From 67dec810eb62dbd7374208fdb75770cb1d617e58 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 24 Jun 2021 17:27:32 -0600
Subject: [PATCH] [Tool] Remove icarus simulator flag; Reduce the file size of
 preconfigured fabric wrapper by only output the necessary force/deposit HDL
 codes

---
 .../verilog_auxiliary_netlists.cpp            |  6 ----
 openfpga/src/fpga_verilog/verilog_constants.h |  4 ---
 .../verilog_preconfig_top_module.cpp          | 30 +++++++++----------
 3 files changed, 14 insertions(+), 26 deletions(-)

diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index 9701a9ace..a3ac9c580 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -206,12 +206,6 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
   /* Print the title */
   print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); 
 
-  /* To enable functional verfication with Icarus */
-  if (true == verilog_testbench_opts.support_icarus_simulator()) {
-    print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1);
-    fp << std::endl;
-  } 
-
   /* To enable auto-checked simulation */
   if ( (true == verilog_testbench_opts.print_preconfig_top_testbench())
     || (true == verilog_testbench_opts.print_top_testbench()) ) {
diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index 4a0ec4908..18e23b721 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -13,10 +13,6 @@ constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to ena
 
 constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
 
-// Icarus variables and flag
-constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
-// End of Icarus variables and flag
-
 constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v";
 constexpr char* TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
 constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index 2e330fc93..e3675428d 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -364,7 +364,8 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
                                                        const ModuleId &top_module,
                                                        const CircuitLibrary& circuit_lib,
                                                        const CircuitModelId& mem_model,
-                                                       const BitstreamManager &bitstream_manager) {
+                                                       const BitstreamManager &bitstream_manager,
+                                                       const bool& support_icarus_simulator) {
 
   /* Skip the datab port if there is only 1 output port in memory model
    * Currently, it assumes that the data output port is always defined while datab is optional
@@ -379,21 +380,17 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream &fp,
 
   print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----"));
 
-  print_verilog_preprocessing_flag(fp, std::string(ICARUS_SIMULATOR_FLAG));
-
   /* Use assign syntax for Icarus simulator */
-  print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module,
-                                                      bitstream_manager,
-                                                      output_datab_bits);
-
-  fp << "`else" << std::endl;
-
-  /* Use assign syntax for Icarus simulator */
-  print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module,
-                                                       bitstream_manager,
-                                                       output_datab_bits);
-
-  print_verilog_endif(fp);
+  if (support_icarus_simulator) {
+    print_verilog_preconfig_top_module_assign_bitstream(fp, module_manager, top_module,
+                                                        bitstream_manager,
+                                                        output_datab_bits);
+  } else {
+    /* Use deposit syntax for other simulators */
+    print_verilog_preconfig_top_module_deposit_bitstream(fp, module_manager, top_module,
+                                                         bitstream_manager,
+                                                         output_datab_bits);
+  }
 
   print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----"));
 }
@@ -505,7 +502,8 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
   /* Assign FPGA internal SRAM/Memory ports to bitstream values */
   print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module,
                                                     circuit_lib, sram_model, 
-                                                    bitstream_manager);
+                                                    bitstream_manager,
+                                                    options.support_icarus_simulator());
 
   /* Add signal initialization: 
    * Bypass writing codes to files due to the autogenerated codes are very large.