[Flow] Extended yosys variable subtitution

This commit is contained in:
Ganesh Gore 2021-03-08 00:21:07 -07:00
parent e6d1ac4a58
commit 67cd9a69b7
2 changed files with 26 additions and 7 deletions

View File

@ -99,6 +99,8 @@ parser.add_argument('--arch_variable_file', type=str, default=None,
# help="Key file for shell")
parser.add_argument('--yosys_tmpl', type=str, default=None,
help="Alternate yosys template, generates top_module.blif")
parser.add_argument('--ys_rewrite_tmpl', type=str, default=None,
help="Alternate yosys template, to rewrite verilog netlist")
parser.add_argument('--disp', action="store_true",
help="Open display while running VPR")
parser.add_argument('--debug', action="store_true",
@ -489,6 +491,9 @@ def run_yosys_with_abc():
"LUT_SIZE": lut_size,
"OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
}
for indx in range(0, len(OpenFPGAArgs), 2):
tmpVar = OpenFPGAArgs[indx][2:].upper()
ys_params[tmpVar] = OpenFPGAArgs[indx+1]
yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
tmpl = Template(open(yosys_template, encoding='utf-8').read())
@ -687,11 +692,20 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"):
def run_rewrite_verilog():
# Rewrite the verilog after optimization
if not args.ys_rewrite_tmpl:
script_cmd = [
"read_blif %s" % args.top_module+".blif",
"write_verilog %s" % args.top_module+"_output_verilog.v"
]
command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
else:
ys_rewrite_params = {
"INPUT_BLIF": args.top_module+".blif",
"OUTPUT_VERILOG": args.top_module+"_output_verilog.v"
}
for indx in range(0, len(OpenFPGAArgs), 2):
tmpVar = OpenFPGAArgs[indx][2:].upper()
ys_rewrite_params[tmpVar] = OpenFPGAArgs[indx+1]
run_command("Yosys", "yosys_rewrite.log", command)

View File

@ -263,6 +263,8 @@ def generate_each_task_actions(taskname):
fallback="top")
CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys",
fallback=ys_for_task_common)
CurrBenchPara["ys_rewrite_script"] = SynthSection.get(bech_name+"_yosys_rewrite",
fallback=ys_for_task_common)
CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width",
fallback=chan_width_common)
@ -381,6 +383,9 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
if benchmark_obj.get("ys_script"):
command += ["--yosys_tmpl", benchmark_obj["ys_script"]]
if benchmark_obj.get("ys_rewrite_script"):
command += ["--ys_rewrite_tmpl", benchmark_obj["ys_rewrite_script"]]
if task_gc.getboolean("power_analysis"):
command += ["--power"]
command += ["--power_tech", task_gc.get("power_tech_file")]