[Flow] Extended yosys variable subtitution

openfpga_flow/scripts/run_fpga_flow.py

@@ -99,6 +99,8 @@ parser.add_argument('--arch_variable_file', type=str, default=None,
 #                     help="Key file for shell")
 parser.add_argument('--yosys_tmpl', type=str, default=None,
                     help="Alternate yosys template, generates top_module.blif")
+parser.add_argument('--ys_rewrite_tmpl', type=str, default=None,
+                    help="Alternate yosys template, to rewrite verilog netlist")
 parser.add_argument('--disp', action="store_true",
                     help="Open display while running VPR")
 parser.add_argument('--debug', action="store_true",
@@ -260,7 +262,7 @@ def main():
         if args.power:
             run_ace2()
             run_pro_blif_3arg()
-        else: 
+        else:
             # Make a copy of the blif file to be compatible with vpr flow
             shutil.copy(args.top_module+'_yosys_out.blif', args.top_module+".blif")
 
@@ -489,6 +491,9 @@ def run_yosys_with_abc():
         "LUT_SIZE": lut_size,
         "OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
     }
+    for indx in range(0, len(OpenFPGAArgs), 2):
+        tmpVar = OpenFPGAArgs[indx][2:].upper()
+        ys_params[tmpVar] = OpenFPGAArgs[indx+1]
     yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
         cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
     tmpl = Template(open(yosys_template, encoding='utf-8').read())
@@ -687,11 +692,20 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"):
 
 def run_rewrite_verilog():
     # Rewrite the verilog after optimization
-    script_cmd = [
+    if not args.ys_rewrite_tmpl:
-        "read_blif %s" % args.top_module+".blif",
+        script_cmd = [
-        "write_verilog %s" % args.top_module+"_output_verilog.v"
+            "read_blif %s" % args.top_module+".blif",
-    ]
+            "write_verilog %s" % args.top_module+"_output_verilog.v"
-    command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
+        ]
+        command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
+    else:
+        ys_rewrite_params = {
+            "INPUT_BLIF": args.top_module+".blif",
+            "OUTPUT_VERILOG": args.top_module+"_output_verilog.v"
+        }
+        for indx in range(0, len(OpenFPGAArgs), 2):
+            tmpVar = OpenFPGAArgs[indx][2:].upper()
+            ys_rewrite_params[tmpVar] = OpenFPGAArgs[indx+1]
     run_command("Yosys", "yosys_rewrite.log", command)
 
 

openfpga_flow/scripts/run_fpga_task.py

@@ -175,7 +175,7 @@ def generate_each_task_actions(taskname):
         curr_task_dir = repo_tasks
     else:
         clean_up_and_exit("Task directory [%s] not found" % curr_task_dir)
-    
+
     os.chdir(curr_task_dir)
 
     curr_task_conf_file = os.path.join(curr_task_dir, "config", "task.conf")
@@ -263,6 +263,8 @@ def generate_each_task_actions(taskname):
                                                        fallback="top")
         CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys",
                                                       fallback=ys_for_task_common)
+        CurrBenchPara["ys_rewrite_script"] = SynthSection.get(bech_name+"_yosys_rewrite",
+                                                      fallback=ys_for_task_common)
         CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width",
                                                        fallback=chan_width_common)
 
@@ -381,6 +383,9 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
     if benchmark_obj.get("ys_script"):
         command += ["--yosys_tmpl", benchmark_obj["ys_script"]]
 
+    if benchmark_obj.get("ys_rewrite_script"):
+        command += ["--ys_rewrite_tmpl", benchmark_obj["ys_rewrite_script"]]
+
     if task_gc.getboolean("power_analysis"):
         command += ["--power"]
         command += ["--power_tech", task_gc.get("power_tech_file")]