diff --git a/openfpga_flow/openfpga_cell_library/verilog/dpram.v b/openfpga_flow/openfpga_cell_library/verilog/dpram.v
index ebc838891..41d63a00f 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/dpram.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/dpram.v
@@ -14,7 +14,7 @@ module dpram (
 	input[0:31] d_in,
 	output[0:31] d_out );
 
-		dual_port_sram memory_0 (
+		dpram_1024x32_core memory_0 (
 			.wclk		(clk),
 			.wen		(wen),
 			.waddr		(waddr),
@@ -26,7 +26,7 @@ module dpram (
 
 endmodule
 
-module dual_port_sram (
+module dpram_1024x32_core (
 	input wclk,
 	input wen,
 	input[0:9] waddr,