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[test] now use correct pcf for clock network testcases

This commit is contained in:
tangxifan 2024-06-29 10:04:03 -07:00
parent 8bc37080fa
commit 67554cb8d8
6 changed files with 8 additions and 4 deletions
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1
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_reset.xml
View File

@ -3,5 +3,6 @@
- the reset signal to the op_reset[0] port of the FPGA fabric - the reset signal to the op_reset[0] port of the FPGA fabric
--> -->
<set_io pin="op_reset[0]" net="reset"/> <set_io pin="op_reset[0]" net="reset"/>
<set_io pin="op_clk[0]" net="clk"/>
</pin_constraints> </pin_constraints>

1
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/pin_constraints_resetb.xml
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@ -3,5 +3,6 @@
- the reset signal to the op_reset[0] port of the FPGA fabric - the reset signal to the op_reset[0] port of the FPGA fabric
--> -->
<set_io pin="op_reset[0]" net="resetb" default_value="1"/> <set_io pin="op_reset[0]" net="resetb" default_value="1"/>
<set_io pin="op_clk[0]" net="clk"/>
</pin_constraints> </pin_constraints>

4
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf
View File

@ -42,11 +42,11 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = counter bench0_top = counter
bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_verilog_testbench_port_mapping= bench0_openfpga_verilog_testbench_port_mapping=
bench1_top = counter bench1_top = counter
bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml
bench1_openfpga_verilog_testbench_port_mapping= bench1_openfpga_verilog_testbench_port_mapping=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_reset.xml
View File

@ -3,5 +3,6 @@
- the reset signal to the op_reset[0] port of the FPGA fabric - the reset signal to the op_reset[0] port of the FPGA fabric
--> -->
<set_io pin="op_reset[0]" net="reset"/> <set_io pin="op_reset[0]" net="reset"/>
<set_io pin="op_clk[0]" net="clk"/>
</pin_constraints> </pin_constraints>

1
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/pin_constraints_resetb.xml
View File

@ -3,5 +3,6 @@
- the reset signal to the op_reset[0] port of the FPGA fabric - the reset signal to the op_reset[0] port of the FPGA fabric
--> -->
<set_io pin="op_reset[0]" net="resetb" default_value="1"/> <set_io pin="op_reset[0]" net="resetb" default_value="1"/>
<set_io pin="op_clk[0]" net="clk"/>
</pin_constraints> </pin_constraints>

4
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf
View File

@ -42,11 +42,11 @@ bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_df
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = counter bench0_top = counter
bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_verilog_testbench_port_mapping= bench0_openfpga_verilog_testbench_port_mapping=
bench1_top = counter bench1_top = counter
bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml
bench1_openfpga_verilog_testbench_port_mapping= bench1_openfpga_verilog_testbench_port_mapping=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]