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[Arch] Use disable_packing in architecture library

This commit is contained in:
tangxifan 2021-02-04 16:29:03 -07:00
parent 2483154c34
commit 66bc370c4d
27 changed files with 52 additions and 52 deletions
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4
openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml
View File

@ -170,7 +170,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -242,7 +242,7 @@
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>

4
openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
View File

@ -170,7 +170,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -242,7 +242,7 @@
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>

4
openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
View File

@ -170,7 +170,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -242,7 +242,7 @@
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>

4
openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
View File

@ -195,7 +195,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -271,7 +271,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
View File

@ -238,7 +238,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -314,7 +314,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml
View File

@ -253,7 +253,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -329,7 +329,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml
View File

@ -265,7 +265,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -341,7 +341,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k4_frac_N4_tileable_lutram_40nm.xml
View File

@ -188,7 +188,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -260,7 +260,7 @@
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>

4
openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -269,7 +269,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -354,7 +354,7 @@
<output name="scout" num_pins="1"/> <output name="scout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<input name="regin" num_pins="1"/> <input name="regin" num_pins="1"/>

2
openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
View File

@ -335,7 +335,7 @@
<output name="scout" num_pins="1"/> <output name="scout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<input name="regin" num_pins="1"/> <input name="regin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -273,7 +273,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -360,7 +360,7 @@
<output name="sc_out" num_pins="1"/> <output name="sc_out" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<input name="reg_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>

4
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -289,7 +289,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -380,7 +380,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="4"/> <input name="in" num_pins="4"/>
<input name="reg_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>

2
openfpga_flow/vpr_arch/k6_N10_40nm.xml
View File

@ -137,7 +137,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml
View File

@ -163,7 +163,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -235,7 +235,7 @@
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml
View File

@ -250,7 +250,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -326,7 +326,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
View File

@ -290,7 +290,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -366,7 +366,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
View File

@ -163,7 +163,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -235,7 +235,7 @@
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
View File

@ -250,7 +250,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -326,7 +326,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
View File

@ -345,7 +345,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -428,7 +428,7 @@
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
View File

@ -290,7 +290,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -366,7 +366,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
View File

@ -358,7 +358,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -434,7 +434,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
View File

@ -327,7 +327,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -403,7 +403,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
View File

@ -294,7 +294,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -370,7 +370,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
View File

@ -290,7 +290,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -366,7 +366,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
View File

@ -297,7 +297,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -373,7 +373,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
View File

@ -290,7 +290,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -366,7 +366,7 @@
<output name="cout" num_pins="1"/> <output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/> <input name="cin" num_pins="1"/>

4
openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
View File

@ -163,7 +163,7 @@
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1"> <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/> <input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/> <output name="inpad" num_pins="1"/>
@ -235,7 +235,7 @@
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Physical mode definition begin (physical implementation of the fle) --> <!-- Physical mode definition begin (physical implementation of the fle) -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disable_packing="true">
<pb_type name="fabric" num_pb="1"> <pb_type name="fabric" num_pb="1">
<input name="in" num_pins="6"/> <input name="in" num_pins="6"/>
<output name="out" num_pins="2"/> <output name="out" num_pins="2"/>