diff --git a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
index d32efd8de..c0d607084 100644
--- a/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
+++ b/openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
@@ -61,60 +61,60 @@
       <io_nmos model_name="nch_25" chan_length="100e-9" min_width="120e-9"/>
       <io_pmos model_name="pch_25" chan_length="100e-9" min_width="120e-9"/>
     </transistors>
-    <module_spice_models>
-      <spice_model type="inv_buf" name="INVTX1" prefix="INVTX1" dump_explicit_port_map="true" is_default="0">
+    <module_circuit_models>
+      <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" dump_explicit_port_map="true" is_default="0">
         <design_technology type="cmos" topology="inverter" size="3" tapered="off" power_gated="true"/>
         <port type="input" prefix="in" size="1" lib_name="I"/>
         <port type="input" prefix="EN" size="1" lib_name="EN" is_global="true" default_val="0" is_config_enable="true"/>
         <port type="input" prefix="ENB" size="1" lib_name="ENB" is_global="true" default_val="1" is_config_enable="true"/>
         <port type="output" prefix="out" size="1" lib_name="Z"/>
-      </spice_model>
-      <spice_model type="inv_buf" name="INVD4BWP" prefix="INVD4BWP" dump_explicit_port_map="true" is_default="0" verilog_netlist="VerilogNetlists/essential_gates.v">
-        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="4"/>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="INVD4BWP" prefix="INVD4BWP" dump_explicit_port_map="true" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
         <port type="input" prefix="in" lib_name="I" size="1"/>
         <port type="output" prefix="out" lib_name="ZN" size="1"/>
-      </spice_model>
-      <spice_model type="inv_buf" name="INVD1BWP" prefix="INVD1BWP" dump_explicit_port_map="true" is_default="0" verilog_netlist="VerilogNetlists/essential_gates.v">
-        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="4"/>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="INVD1BWP" prefix="INVD1BWP" dump_explicit_port_map="true" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
         <port type="input" prefix="in" lib_name="I" size="1"/>
         <port type="output" prefix="out" lib_name="ZN" size="1"/>
-      </spice_model>
-      <spice_model type="inv_buf" name="INVD2BWP" prefix="INVD2BWP" dump_explicit_port_map="true" is_default="0" verilog_netlist="VerilogNetlists/essential_gates.v">
-        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="4"/>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="INVD2BWP" prefix="INVD2BWP" dump_explicit_port_map="true" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
         <port type="input" prefix="in" lib_name="I" size="1"/>
         <port type="output" prefix="out" lib_name="ZN" size="1"/>
-      </spice_model>
-      <spice_model type="inv_buf" name="INVD3BWP" prefix="INVD3BWP" dump_explicit_port_map="true" is_default="0" verilog_netlist="VerilogNetlists/essential_gates.v">
-        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="4"/>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="INVD3BWP" prefix="INVD3BWP" dump_explicit_port_map="true" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
         <port type="input" prefix="in" lib_name="I" size="1"/>
         <port type="output" prefix="out" lib_name="ZN" size="1"/>
-      </spice_model>
-      <spice_model type="inv_buf" name="BUFFD2BWP" prefix="BUFFD2BWP" dump_explicit_port_map="true" is_default="0" verilog_netlist="VerilogNetlists/essential_gates.v">
-        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="4"/>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="BUFFD2BWP" prefix="BUFFD2BWP" dump_explicit_port_map="true" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
         <port type="input" prefix="in" lib_name="I" size="1"/>
         <port type="output" prefix="out" lib_name="Z" size="1"/>
-      </spice_model>
-      <spice_model type="inv_buf" name="BUFFD3BWP" prefix="BUFFD3BWP" dump_explicit_port_map="true" is_default="0" verilog_netlist="VerilogNetlists/essential_gates.v">
-        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="4"/>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="BUFFD3BWP" prefix="BUFFD3BWP" dump_explicit_port_map="true" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
         <port type="input" prefix="in" lib_name="I" size="1"/>
         <port type="output" prefix="out" lib_name="Z" size="1"/>
-      </spice_model>
-      <spice_model type="inv_buf" name="BUFFD1BWP" prefix="BUFFD1BWP" dump_explicit_port_map="true" is_default="0" verilog_netlist="VerilogNetlists/essential_gates.v">
-        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="4"/>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="BUFFD1BWP" prefix="BUFFD1BWP" dump_explicit_port_map="true" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
         <port type="input" prefix="in" lib_name="I" size="1"/>
         <port type="output" prefix="out" lib_name="Z" size="1"/>
-      </spice_model>
-      <spice_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
-        <design_technology type="cmos" topology="buffer" size="3" tapered="on" tap_buf_level="2" f_per_stage="4"/>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="3" tapered="on" tap_drive_level="2" f_per_stage="4"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="1"/>
-      </spice_model>
-      <spice_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
-        <design_technology type="cmos" topology="buffer" size="3" tapered="on" tap_buf_level="3" f_per_stage="4"/>
+      </circuit_model>
+      <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
+        <design_technology type="cmos" topology="buffer" size="3" tapered="on" tap_drive_level="3" f_per_stage="4"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="1"/>
-      </spice_model>
-      <spice_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
+      </circuit_model>
+      <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
         <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
         <input_buffer exist="off"/>
         <output_buffer exist="off"/>
@@ -122,8 +122,8 @@
         <port type="input" prefix="sel" size="1"/>
         <port type="input" prefix="selb" size="1"/>
         <port type="output" prefix="out" size="1"/>
-      </spice_model>
-      <spice_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
+      </circuit_model>
+      <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
         <design_technology type="cmos"/>
         <input_buffer exist="off"/>
         <output_buffer exist="off"/>
@@ -131,8 +131,8 @@
         <port type="output" prefix="out" size="1"/>
         <wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
         <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-      </spice_model>
-      <spice_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
+      </circuit_model>
+      <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
         <design_technology type="cmos"/>
         <input_buffer exist="off"/>
         <output_buffer exist="off"/>
@@ -140,126 +140,126 @@
         <port type="output" prefix="out" size="1"/>
         <wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
         <!-- model_type could be T, res_val cap_val should be defined -->
-      </spice_model>
-      <spice_model type="mux" name="mux_1level" prefix="mux_1level" is_default="1" dump_structural_verilog="true">
+      </circuit_model>
+      <circuit_model type="mux" name="mux_1level" prefix="mux_1level" is_default="1" dump_structural_verilog="true">
         <!-- <design_technology type="cmos" structure="one-level"/?]> -->
         <design_technology type="rram" ron="2e3" roff="30e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2" structure="one-level" advanced_rram_design="true"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="INVD1BWP"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="INVD1BWP"/>
         <!--mux2to1 subckt_name="mux2to1"/-->
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="input" prefix="EN" size="1" is_global="true" default_val="0" is_config_enable="true"/>
         <port type="input" prefix="ENB" size="1" is_global="true" default_val="1" is_config_enable="true"/>
         <port type="output" prefix="out" size="1"/>
-        <port type="sram" prefix="sram" size="1" spice_model_name="sram6T_rram"/>
-      </spice_model>
-      <spice_model type="mux" name="mux_1level_tapbuf4" prefix="mux_1level_tapbuf4" is_default="0" dump_structural_verilog="true">
+        <port type="sram" prefix="sram" size="1" circuit_model_name="sram6T_rram"/>
+      </circuit_model>
+      <circuit_model type="mux" name="mux_1level_tapbuf4" prefix="mux_1level_tapbuf4" is_default="0" dump_structural_verilog="true">
         <!-- <design_technology type="cmos" structure="one-level"/?]> -->
         <design_technology type="rram" ron="2e3" roff="30e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2" structure="one-level" advanced_rram_design="true"/>
-        <input_buffer exist="on" spice_model_name="INVTX1"/>
-        <output_buffer exist="on" spice_model_name="tap_buf4"/>
+        <input_buffer exist="on" circuit_model_name="INVTX1"/>
+        <output_buffer exist="on" circuit_model_name="tap_buf4"/>
         <!--mux2to1 subckt_name="mux2to1"/-->
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="input" prefix="EN" size="1" is_global="true" default_val="0" is_config_enable="true"/>
         <port type="input" prefix="ENB" size="1" is_global="true" default_val="1" is_config_enable="true"/>
         <port type="output" prefix="out" size="1"/>
-        <port type="sram" prefix="sram" size="1" spice_model_name="sram6T_rram"/>
-      </spice_model>
+        <port type="sram" prefix="sram" size="1" circuit_model_name="sram6T_rram"/>
+      </circuit_model>
       <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-      <spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="VerilogNetlists/ff.v">
+      <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/ff.v">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <output_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <output_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="D" size="1"/>
         <port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
         <port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
         <port type="output" prefix="Q" size="1"/>
         <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
-      </spice_model>
-      <spice_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
+      </circuit_model>
+      <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <output_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <lut_input_buffer exist="on" spice_model_name="BUFFD3BWP"/>
-        <!-- <lut_intermediate_buffer exist="on" spice_model_name="BUFFD1BWP" location_map="-1-1-"/> -->
-        <lut_input_inverter exist="on" spice_model_name="INVD3BWP"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <output_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <lut_input_buffer exist="on" circuit_model_name="BUFFD3BWP"/>
+        <!-- <lut_intermediate_buffer exist="on" circuit_model_name="BUFFD1BWP" location_map="-1-1-"/> -->
+        <lut_input_inverter exist="on" circuit_model_name="INVD3BWP"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="6"/>
         <port type="output" prefix="out" size="1"/>
-        <port type="sram" prefix="sram" size="64" spice_model_name="sram6T_rram" default_val="1"/>
-      </spice_model>
-      <spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="VerilogNetlists/sram.v">
+        <port type="sram" prefix="sram" size="64" circuit_model_name="sram6T_rram" default_val="1"/>
+      </circuit_model>
+      <circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <output_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <output_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="2"/>
-      </spice_model>
-      <spice_model type="sram" name="sram6T_rram" prefix="nvsram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="VerilogNetlists/sram.v">
+      </circuit_model>
+      <circuit_model type="sram" name="sram6T_rram" prefix="nvsram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
         <!--design_technology type="cmos"/-->
         <design_technology type="rram" ron="3e3" roff="1e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2"/>
-        <input_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <output_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <output_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="input" prefix="read" size="1" is_global="true" default_val="0" />
         <port type="input" prefix="nequalize" size="1" is_global="true" default_val="1" />
         <port type="output" prefix="out" size="2"/>
-        <port type="bl" prefix="bl" size="3" default_val="0" inv_spice_model_name="INVD1BWP"/>
-        <port type="wl" prefix="wl" size="3" default_val="0" inv_spice_model_name="INVD1BWP"/>
-      </spice_model>
-      <spice_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="VerilogNetlists/sram.v">
+        <port type="bl" prefix="bl" size="3" default_val="0" inv_circuit_model_name="INVD1BWP"/>
+        <port type="wl" prefix="wl" size="3" default_val="0" inv_circuit_model_name="INVD1BWP"/>
+      </circuit_model>
+      <circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <output_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <output_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="in" size="1"/>
         <port type="input" prefix="read" size="1" is_global="true" default_val="0" />
         <port type="input" prefix="nequalize" size="1" is_global="true" default_val="0" />
         <port type="output" prefix="out" size="2"/>
         <port type="bl" prefix="bl" size="1"/>
         <port type="wl" prefix="wl" size="1"/>
-      </spice_model>
+      </circuit_model>
       <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-      <spice_model type="sff" name="sc_ff" prefix="scff" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="VerilogNetlists/ff.v">
+      <circuit_model type="sff" name="sc_ff" prefix="scff" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/ff.v">
         <design_technology type="cmos"/>
-        <input_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <output_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <output_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="input" prefix="D" size="1"/>
         <port type="input" prefix="Set" size="1"/>
         <port type="input" prefix="Reset" size="1"/>
         <port type="output" prefix="Q" size="1"/>
         <port type="output" prefix="Qb" size="1"/>
         <port type="clock" prefix="clk" size="1"/>
-      </spice_model>
-      <spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="VerilogNetlists/io.v">
+      </circuit_model>
+      <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/io.v">
         <!--design_technology type="cmos"/-->
         <design_technology type="rram" ron="3e3" roff="1e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2"/>
-        <input_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <output_buffer exist="on" spice_model_name="INVD1BWP"/>
-        <pass_gate_logic spice_model_name="TGATE"/>
+        <input_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <output_buffer exist="on" circuit_model_name="INVD1BWP"/>
+        <pass_gate_logic circuit_model_name="TGATE"/>
         <port type="inout" prefix="pad" size="1"/>
-        <port type="sram" prefix="en" size="1" mode_select="true" spice_model_name="sram6T_rram" default_val="1"/>
+        <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_rram" default_val="1"/>
         <port type="input" prefix="outpad" size="1"/>
         <port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
         <port type="output" prefix="inpad" size="1"/>
-      </spice_model>
-    </module_spice_models>
+      </circuit_model>
+    </module_circuit_models>
   </spice_settings>
   <device>
     <sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="3"/>
     <timing C_ipin_cblock="596e-18" T_ipin_cblock="45.54e-12"/>
     <area grid_logic_tile_area="0"/>
-    <!--sram area="6" organization="standalone" spice_model_name="sram6T"-->
-    <!--sram area="6" organization="scan-chain" spice_model_name="sc_dff"-->
+    <!--sram area="6" organization="standalone" circuit_model_name="sram6T"-->
+    <!--sram area="6" organization="scan-chain" circuit_model_name="sc_dff"-->
     <sram area="6">
-      <verilog organization="memory-bank" spice_model_name="sram6T_rram" />
-      <spice organization="standalone" spice_model_name="sram6T" />
+      <verilog organization="memory-bank" circuit_model_name="sram6T_rram" />
+      <spice organization="standalone" circuit_model_name="sram6T" />
     </sram>
     <chan_width_distr>
       <io width="1.000000"/>
@@ -270,7 +270,7 @@
   </device>
 
   <cblocks>
-    <switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="45.54e-12" mux_trans_size="1.5" buf_size="4" spice_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
+    <switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="45.54e-12" mux_trans_size="1.5" buf_size="4" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
     </switch>
   </cblocks>
   <switchlist>
@@ -287,28 +287,28 @@
 	       2.5x when looking up in Jeff's tables.
 	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
 	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="sb_mux_L4" R="106" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" spice_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
+    <switch type="mux" name="sb_mux_L4" R="106" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
     </switch>
-    <switch type="mux" name="sb_mux_L2" R="121" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" spice_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
+    <switch type="mux" name="sb_mux_L2" R="121" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
     </switch>
-    <switch type="mux" name="sb_mux_L1" R="147" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" spice_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
+    <switch type="mux" name="sb_mux_L1" R="147" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
     </switch>
   </switchlist>
   <segmentlist>
     <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
 			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
 			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
+    <segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
       <mux name="sb_mux_L4"/>
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>
     </segment>
-    <segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
+    <segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
       <mux name="sb_mux_L4"/>
       <sb type="pattern">1 1 1</sb>
       <cb type="pattern">1 1</cb>
     </segment>
-    <segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
+    <segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
       <mux name="sb_mux_L4"/>
       <sb type="pattern">1 1</sb>
       <cb type="pattern">1</cb>
@@ -326,7 +326,7 @@
 
       <!-- physical design description -->
       <mode name="io_phy" disabled_in_packing="true">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1" spice_model_name="iopad" mode_bits="1">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad" mode_bits="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
         </pb_type>
@@ -410,7 +410,7 @@
       <!-- Describe fracturable logic element.
              Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
              The outputs of the fracturable logic element can be optionally registered
-        For spice modeling: in each primitive pb_type, user should define a spice_model_name that linkes to the
+        For spice modeling: in each primitive pb_type, user should define a circuit_model_name that linkes to the
         defined spice models
         -->
       <pb_type name="fle" num_pb="10" idle_mode_name="n1_lut6" physical_mode_name="n1_lut6">
@@ -425,7 +425,7 @@
             <output name="out" num_pins="1"/>
             <clock name="clk" num_pins="1"/>
             <!-- Define LUT -->
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" spice_model_name="lut6">
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut6">
               <input name="in" num_pins="6" port_class="lut_in"/>
               <output name="out" num_pins="1" port_class="lut_out"/>
               <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
@@ -439,7 +439,7 @@
             </pb_type>
 
             <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" spice_model_name="static_dff">
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
               <input name="D" num_pins="1" port_class="D"/>
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
@@ -454,7 +454,7 @@
                 <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
               </direct>
               <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out" spice_model_name="mux_1level">
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out" circuit_model_name="mux_1level">
                 <delay_constant max="2.736e-10" in_port="lut6.out" out_port="ble6.out" />
                 <delay_constant max="2.736e-10" in_port="ff.Q" out_port="ble6.out" />
               </mux>
@@ -478,7 +478,7 @@
 		     Since all our outputs LUT outputs go to a BLE output, and have a delay of
 		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
 		     to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in" spice_model_name="mux_1level">
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in" circuit_model_name="mux_1level">
           <delay_constant max="1.0877e-09" in_port="clb.I" out_port="fle[9:0].in" />
           <delay_constant max="1.0877e-09" in_port="fle[9:0].out" out_port="fle[9:0].in" />
         </complete>