diff --git a/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp b/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp
index 135e38361..c6ca09012 100644
--- a/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp
+++ b/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp
@@ -89,14 +89,6 @@ static void read_xml_tile_global_port_annotation(
     get_attribute(xml_tile, "is_clock", loc_data, pugiutil::ReqOpt::OPTIONAL)
       .as_bool(false));
 
-  /* Get clock tree attributes if this is a clock */
-  if (tile_annotation.global_port_is_clock(tile_global_port_id)) {
-    tile_annotation.set_global_port_clock_arch_tree_name(
-      tile_global_port_id, get_attribute(xml_tile, "clock_arch_tree_name",
-                                         loc_data, pugiutil::ReqOpt::OPTIONAL)
-                             .as_string());
-  }
-
   /* Get is_set attributes */
   tile_annotation.set_global_port_is_set(
     tile_global_port_id,
@@ -109,6 +101,16 @@ static void read_xml_tile_global_port_annotation(
     get_attribute(xml_tile, "is_reset", loc_data, pugiutil::ReqOpt::OPTIONAL)
       .as_bool(false));
 
+  /* Get clock tree attributes if this is a clock, reset or set */
+  if (tile_annotation.global_port_is_clock(tile_global_port_id)
+   || tile_annotation.global_port_is_reset(tile_global_port_id)
+   || tile_annotation.global_port_is_set(tile_global_port_id)) {
+    tile_annotation.set_global_port_clock_arch_tree_name(
+      tile_global_port_id, get_attribute(xml_tile, "clock_arch_tree_name",
+                                         loc_data, pugiutil::ReqOpt::OPTIONAL)
+                             .as_string());
+  }
+
   /* Get default_value attributes */
   tile_annotation.set_global_port_default_value(
     tile_global_port_id,