From 66a50742fc4501f7de40c3b66ff22d9d3d752979 Mon Sep 17 00:00:00 2001 From: tangxifan <tangxifan@gmail.com> Date: Wed, 15 Jul 2020 11:56:11 -0600 Subject: [PATCH] use configuration chain in the k4k4 test case to speed up CI --- .../fpga_verilog/verilog_top_testbench.cpp | 9 +++++++- .../openfpga_arch/k4_N4_40nm_cc_openfpga.xml | 23 ++++++------------- 2 files changed, 15 insertions(+), 17 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 00e6a80f5..0f5640618 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -576,6 +576,7 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz case CONFIG_MEM_SCAN_CHAIN: /* For fast configuraiton, the bitstream size counts from the first bit '1' */ if (true == fast_configuration) { + size_t full_num_config_clock_cycles = num_config_clock_cycles; size_t num_bits_to_skip = 0; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { @@ -583,7 +584,13 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz } num_bits_to_skip++; } - num_config_clock_cycles -= num_bits_to_skip; + + num_config_clock_cycles = full_num_config_clock_cycles - num_bits_to_skip; + + VTR_LOG("Fast configuration reduces number of configuration clock cycles from %lu to %lu (compression_rate = %f%)\n", + full_num_config_clock_cycles, + num_config_clock_cycles, + 100. * ((float)num_config_clock_cycles / (float)full_num_config_clock_cycles - 1.)); } break; case CONFIG_MEM_MEMORY_BANK: diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index 95359f565..f1db02ad1 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -96,8 +96,8 @@ <port type="output" prefix="out" size="1"/> <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> </circuit_model> - <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true"> - <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> + <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true"> + <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/> <pass_gate_logic circuit_model_name="TGATE"/> @@ -105,17 +105,8 @@ <port type="output" prefix="out" size="1"/> <port type="sram" prefix="sram" size="1"/> </circuit_model> - <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true"> - <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/> - <input_buffer exist="true" circuit_model_name="INVTX1"/> - <output_buffer exist="true" circuit_model_name="tap_buf4"/> - <pass_gate_logic circuit_model_name="TGATE"/> - <port type="input" prefix="in" size="1"/> - <port type="output" prefix="out" size="1"/> - <port type="sram" prefix="sram" size="1"/> - </circuit_model> - <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true"> - <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/> + <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true"> + <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="tap_buf4"/> <pass_gate_logic circuit_model_name="TGATE"/> @@ -170,10 +161,10 @@ <organization type="scan_chain" circuit_model_name="sc_dff_compact"/> </configuration_protocol> <connection_block> - <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/> + <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/> </connection_block> <switch_block> - <switch name="0" circuit_model_name="mux_2level_tapbuf"/> + <switch name="0" circuit_model_name="mux_tree_tapbuf"/> </switch_block> <routing_segment> <segment name="L4" circuit_model_name="chan_segment"/> @@ -190,7 +181,7 @@ <!-- physical mode will be the default mode if not specified --> <pb_type name="clb"> <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model --> - <interconnect name="crossbar" circuit_model_name="mux_2level"/> + <interconnect name="crossbar" circuit_model_name="mux_tree"/> </pb_type> <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/> <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>