optimizing memory efficiency by reserving nets in module manager

openfpga/src/fabric/build_top_module.cpp

@@ -342,6 +342,9 @@ void build_top_module(ModuleManager& module_manager,
   cb_instance_ids[CHANX] = add_top_module_connection_block_instances(module_manager, top_module, device_rr_gsb, CHANX, compact_routing_hierarchy);
   cb_instance_ids[CHANY] = add_top_module_connection_block_instances(module_manager, top_module, device_rr_gsb, CHANY, compact_routing_hierarchy);
 
+  /* Reserve nets to be memory efficient */
+  reserve_module_manager_module_nets(module_manager, top_module);
+
   /* Add module nets to connect the sub modules */
   add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module, 
                                              grids, grid_instance_ids, 

openfpga/src/fabric/module_manager.cpp

@@ -638,6 +638,27 @@ void ModuleManager::reserve_configurable_child(const ModuleId& parent_module,
   }
 }
 
+void ModuleManager::reserve_module_nets(const ModuleId& module,
+                                        const size_t& num_nets) {
+  /* Validate the module id */
+  VTR_ASSERT ( valid_module_id(module) );
+
+  net_ids_[module].reserve(num_nets);
+
+  net_names_[module].reserve(num_nets);
+  net_src_ids_[module].reserve(num_nets);
+  net_src_module_ids_[module].reserve(num_nets);
+  net_src_instance_ids_[module].reserve(num_nets);
+  net_src_port_ids_[module].reserve(num_nets);
+  net_src_pin_ids_[module].reserve(num_nets);
+
+  net_sink_ids_[module].reserve(num_nets);
+  net_sink_module_ids_[module].reserve(num_nets);
+  net_sink_instance_ids_[module].reserve(num_nets);
+  net_sink_port_ids_[module].reserve(num_nets);
+  net_sink_pin_ids_[module].reserve(num_nets);
+}
+
 /* Add a net to the connection graph of the module */ 
 ModuleNetId ModuleManager::create_module_net(const ModuleId& module) {
   /* Validate the module id */

openfpga/src/fabric/module_manager.h

@@ -161,6 +161,11 @@ class ModuleManager {
      */
     void reserve_configurable_child(const ModuleId& module, const size_t& num_children);
 
+    /* Reserved a number of module nets for a given module
+     * for memory efficiency
+     */
+    void reserve_module_nets(const ModuleId& module, const size_t& num_nets);
+
     /* Add a net to the connection graph of the module */ 
     ModuleNetId create_module_net(const ModuleId& module);
     /* Set the name of net */

openfpga/src/utils/module_manager_utils.cpp

@@ -26,6 +26,56 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/******************************************************************************
+ * Reserved a number of module nets for a given module
+ * based on the number of output ports of its child modules
+ * for memory efficiency
+ ******************************************************************************/
+void reserve_module_manager_module_nets(ModuleManager& module_manager, 
+                                        const ModuleId& parent_module) {
+  size_t num_nets = 0;
+
+  /* Collect the driver port types for parent module*/
+  std::vector<ModuleManager::e_module_port_type> driver_port_types;
+  driver_port_types.push_back(ModuleManager::MODULE_GLOBAL_PORT);
+  driver_port_types.push_back(ModuleManager::MODULE_GPIN_PORT);
+  driver_port_types.push_back(ModuleManager::MODULE_GPIO_PORT);
+  driver_port_types.push_back(ModuleManager::MODULE_INOUT_PORT);
+  driver_port_types.push_back(ModuleManager::MODULE_INPUT_PORT);
+  driver_port_types.push_back(ModuleManager::MODULE_CLOCK_PORT);
+
+  /* The number of nets depends on the sizes of input ports of parent module */
+  for (const auto& port_type : driver_port_types) {
+    for (const BasicPort& port : module_manager.module_ports_by_type(parent_module, port_type)) {
+      num_nets += port.get_width();
+    }
+  }
+
+  /* Collect the output port types */
+  std::vector<ModuleManager::e_module_port_type> output_port_types;
+  output_port_types.push_back(ModuleManager::MODULE_GPOUT_PORT);
+  output_port_types.push_back(ModuleManager::MODULE_OUTPUT_PORT);
+  
+  for (const ModuleId& child_module : module_manager.child_modules(parent_module)) {
+    /* The number of nets depends on the sizes of output ports of 
+     * each instanciated child module
+     */
+    size_t num_instances = module_manager.num_instance(parent_module, child_module);
+
+    /* Sum up the port sizes for all the output ports */
+    size_t total_output_port_sizes = 0;
+    for (const auto& port_type : output_port_types) {
+      for (const BasicPort& port : module_manager.module_ports_by_type(child_module, port_type)) {
+        total_output_port_sizes += port.get_width();
+      }
+    }
+
+    num_nets += total_output_port_sizes * num_instances;
+  }
+  
+  module_manager.reserve_module_nets(parent_module, num_nets);
+}
+
 /******************************************************************************
  * Add a module to the module manager based on the circuit-level
  * description of a circuit model

openfpga/src/utils/module_manager_utils.h

@@ -31,6 +31,9 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+void reserve_module_manager_module_nets(ModuleManager& module_manager, 
+                                        const ModuleId& module);
+
 ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, 
                                              const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model,
                                              const std::string& module_name);