diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
index a7e400c84..698aa30fd 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -72,6 +72,8 @@ static int update_cluster_pin_global_net_with_post_routing_results(
      * Get the offset of the pin index in the port, based on which we can infer
      * the pin index in the context of logical block
      */
+    VTR_LOG("Searching for a candidate pin to accomodate global net '%s' was lost during routing optimization\n",
+            clustering_ctx.clb_nlist.net_name(global_net_id).c_str());
     size_t cand_pin_start = pb_type_pin - pb_graph_pin->pin_number;
     size_t cand_pin_end = cand_pin_start + pb_graph_pin->port->num_pins;
     bool found_cand = false;
@@ -81,7 +83,7 @@ static int update_cluster_pin_global_net_with_post_routing_results(
         clustering_ctx.clb_nlist.block_net(blk_id, cand_pin);
       const t_pb_graph_pin* cand_pb_graph_pin =
         get_pb_graph_node_pin_from_block_pin(blk_id, cand_pin);
-      if (!clustering_annotation.is_net_renamed(blk_id, cand_pin)) {
+      if (clustering_annotation.is_net_renamed(blk_id, cand_pin)) {
         cand_pin_net_id = clustering_annotation.net(blk_id, cand_pin);
       }
       if (clustering_ctx.clb_nlist.valid_net_id(cand_pin_net_id)) {