refactorint net addition for configuration signals in module graph
This commit is contained in:
tangxifan
parent
c9950162d1
commit
663b1b7665
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@ -92,6 +92,25 @@ std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary&
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return regular_sram_ports;
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}
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/********************************************************************
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* Find mode select sram ports of a circuit model
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*******************************************************************/
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std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true);
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std::vector<CircuitPortId> mode_select_sram_ports;
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for (const auto& port : sram_ports) {
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if (false == circuit_lib.port_is_mode_select(port)) {
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continue;
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}
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mode_select_sram_ports.push_back(port);
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}
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return mode_select_sram_ports;
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}
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/********************************************************************
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* Find the number of shared configuration bits for a ReRAM circuit
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* TODO: this function is subjected to be changed due to ReRAM-based SRAM cell design!!!
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@ -17,6 +17,9 @@ std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circu
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std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model);
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std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model);
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size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const e_sram_orgz& sram_orgz_type);
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@ -12,10 +12,12 @@
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#include "spice_types.h"
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#include "circuit_library.h"
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#include "circuit_library_utils.h"
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#include "module_manager.h"
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_pbtypes_utils.h"
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#include "fpga_x2p_mem_utils.h"
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#include "module_manager_utils.h"
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@ -397,3 +399,233 @@ void add_primitive_pb_type_module_nets(ModuleManager& module_manager,
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}
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}
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/********************************************************************
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* Add the port-to-port connection between a logic module
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* and a memory module
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* Create nets to wire SRAM ports between logic module and memory module
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*
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* The information about SRAM ports of logic module are stored in the
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* mem_output_bus_ports, where element [0] denotes the SRAM port while
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* element [1] denotes the SRAMb port
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*
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* +---------+ +--------+
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* | | regular SRAM port | |
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* | Logic |-----------------------+ | Memory |
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* | Module | mode-select SRAM port |->| Module |
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* | |-----------------------+ | |
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* +---------+ +--------+
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*
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* There could be multiple SRAM ports of logic module, which are wired to
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* the SRAM ports of memory module
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*
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* Note: this function SHOULD be called after the pb_type_module is created
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* and its child module (logic_module and memory_module) is created!
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*
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* Note: this function only handle either SRAM or SRAMb ports.
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* So, this function may be called twice to complete the wiring
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*******************************************************************/
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static
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void add_module_nets_between_logic_and_memory_sram_ports(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const ModuleId& logic_module,
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const size_t& logic_instance_id,
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const ModuleId& memory_module,
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const size_t& memory_instance_id,
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const std::vector<ModulePortId>& logic_module_sram_port_ids,
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const ModulePortId& mem_module_sram_port_id) {
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/* Find mem_output_bus ports in logic module */
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std::vector<BasicPort> logic_module_sram_ports;
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for (const ModulePortId& logic_module_sram_port_id : logic_module_sram_port_ids) {
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logic_module_sram_ports.push_back(module_manager.module_port(logic_module, logic_module_sram_port_id));
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}
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/* Create a list of virtual ports to align with the SRAM port of logic module
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* Physical ports:
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*
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* logic_module_sram_port[0] logic_module_sram_port[1]
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*
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* LSB[0]------------>MSB[0] LSB------------------>MSB
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*
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* memory_sram_port
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* LSBY---------------------------------------------->MSBY
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*
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* Virtual ports:
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* mem_module_sram_port[0] mem_module_sram_port[1]
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* LSBY--------------->MSBX MSBX+1------------------>MSBY
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*
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*/
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BasicPort mem_module_port = module_manager.module_port(memory_module, mem_module_sram_port_id);
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std::vector<BasicPort> virtual_mem_module_ports;
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/* Create a counter for the LSB of virtual ports */
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size_t port_lsb = 0;
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for (const BasicPort& logic_module_sram_port : logic_module_sram_ports) {
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BasicPort virtual_port;
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virtual_port.set_name(mem_module_port.get_name());
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virtual_port.set_width(port_lsb, port_lsb + logic_module_sram_port.get_width() - 1);
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virtual_mem_module_ports.push_back(virtual_port);
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port_lsb = virtual_port.get_msb() + 1;
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}
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/* port_lsb should be aligned with the MSB of memory_sram_port */
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VTR_ASSERT(port_lsb == mem_module_port.get_msb() + 1);
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/* Wire port to port */
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for (size_t port_index = 0; port_index < logic_module_sram_ports.size(); ++port_index) {
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/* Create a net for each pin */
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for (size_t pin_id = 0; pin_id < logic_module_sram_ports[port_index].pins().size(); ++pin_id) {
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ModuleNetId net = module_manager.create_module_net(parent_module);
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/* Add net source */
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module_manager.add_module_net_source(parent_module, net, logic_module, logic_instance_id, logic_module_sram_port_ids[port_index], logic_module_sram_ports[port_index].pins()[pin_id]);
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/* Add net sink */
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module_manager.add_module_net_sink(parent_module, net, memory_module, memory_instance_id, mem_module_sram_port_id, virtual_mem_module_ports[port_index].pins()[pin_id]);
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}
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}
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}
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/********************************************************************
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* Add the port-to-port connection between a logic module
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* and a memory module
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* Create nets to wire SRAM ports between logic module and memory module
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*
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*
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* +---------+ +--------+
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* | | SRAM ports | |
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* | Logic |----------------------->| Memory |
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* | Module | SRAMb ports | Module |
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* | |----------------------->| |
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* +---------+ +--------+
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*
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* Note: this function SHOULD be called after the pb_type_module is created
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* and its child module (logic_module and memory_module) is created!
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*
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*******************************************************************/
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void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const ModuleId& logic_module,
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const size_t& logic_instance_id,
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const ModuleId& memory_module,
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const size_t& memory_instance_id,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& logic_model) {
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/* Connect SRAM port */
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/* Find SRAM ports in the circuit model for logic module */
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std::vector<std::string> logic_model_sram_port_names;
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/* Regular sram port goes first */
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for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) {
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logic_model_sram_port_names.push_back(circuit_lib.port_lib_name(regular_sram_port));
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}
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/* Mode-select sram port goes first */
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for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) {
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logic_model_sram_port_names.push_back(circuit_lib.port_lib_name(mode_select_sram_port));
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}
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/* Find the port ids in the memory */
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std::vector<ModulePortId> logic_module_sram_port_ids;
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for (const std::string& logic_model_sram_port_name : logic_model_sram_port_names) {
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/* Skip non-exist ports */
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if (ModulePortId::INVALID() == module_manager.find_module_port(logic_module, logic_model_sram_port_name)) {
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continue;
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}
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logic_module_sram_port_ids.push_back(module_manager.find_module_port(logic_module, logic_model_sram_port_name));
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}
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/* Get the SRAM port name of memory model */
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/* TODO: this should be a constant expression and it should be the same for all the memory module! */
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std::string memory_model_sram_port_name = generate_configuration_chain_data_out_name();
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/* Find the corresponding ports in memory module */
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ModulePortId mem_module_sram_port_id = module_manager.find_module_port(memory_module, memory_model_sram_port_name);
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/* Do wiring only when we have sram ports */
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if ( (false == logic_module_sram_port_ids.empty())
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|| (ModulePortId::INVALID() == mem_module_sram_port_id) ) {
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add_module_nets_between_logic_and_memory_sram_ports(module_manager, parent_module,
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logic_module, logic_instance_id,
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memory_module, memory_instance_id,
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logic_module_sram_port_ids, mem_module_sram_port_id);
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}
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/* Connect SRAMb port */
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/* Find SRAM ports in the circuit model for logic module */
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std::vector<std::string> logic_model_sramb_port_names;
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/* Regular sram port goes first */
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for (CircuitPortId regular_sram_port : find_circuit_regular_sram_ports(circuit_lib, logic_model)) {
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logic_model_sramb_port_names.push_back(circuit_lib.port_lib_name(regular_sram_port) + std::string("_inv"));
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}
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/* Mode-select sram port goes first */
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for (CircuitPortId mode_select_sram_port : find_circuit_mode_select_sram_ports(circuit_lib, logic_model)) {
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logic_model_sramb_port_names.push_back(circuit_lib.port_lib_name(mode_select_sram_port) + std::string("_inv"));
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}
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/* Find the port ids in the memory */
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std::vector<ModulePortId> logic_module_sramb_port_ids;
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for (const std::string& logic_model_sramb_port_name : logic_model_sramb_port_names) {
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/* Skip non-exist ports */
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if (ModulePortId::INVALID() == module_manager.find_module_port(logic_module, logic_model_sramb_port_name)) {
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continue;
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}
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logic_module_sramb_port_ids.push_back(module_manager.find_module_port(logic_module, logic_model_sramb_port_name));
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}
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/* Get the SRAM port name of memory model */
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std::string memory_model_sramb_port_name = generate_configuration_chain_inverted_data_out_name();
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/* Find the corresponding ports in memory module */
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ModulePortId mem_module_sramb_port_id = module_manager.find_module_port(memory_module, memory_model_sramb_port_name);
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/* Do wiring only when we have sramb ports */
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if ( (false == logic_module_sramb_port_ids.empty())
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|| (ModulePortId::INVALID() == mem_module_sramb_port_id) ) {
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add_module_nets_between_logic_and_memory_sram_ports(module_manager, parent_module,
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logic_module, logic_instance_id,
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memory_module, memory_instance_id,
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logic_module_sramb_port_ids, mem_module_sramb_port_id);
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}
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}
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/********************************************************************
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* TODO:
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* Add the port-to-port connection between a logic module
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* and a memory module inside a primitive module
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*
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* Create nets to wire the control signals of memory module to
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* the configuration ports of primitive module
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*
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* Primitive module
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* +----------------------------+
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* | +--------+ |
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* config | | | |
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* ports --->|--------------->| Memory | |
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* | | Module | |
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* | | | |
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* | +--------+ |
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* +----------------------------+
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* The detailed config ports really depend on the type
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* of SRAM organization.
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*
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* Note: this function SHOULD be called after the pb_type_module is created
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* and its child module (logic_module and memory_module) is created!
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*******************************************************************/
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/********************************************************************
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* TODO:
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* Add the port-to-port connection between a logic module
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* and a memory module inside a primitive module
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*
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* Create nets to wire the formal verification ports of
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* primitive module to SRAM ports of logic module
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*
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* Primitive module
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*
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* formal_port_sram
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* +-----------------------------------------------+
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* | ^ |
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* | +---------+ | +--------+ |
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* | | | SRAM | | | |
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* | | Logic |--------+--->| Memory | |
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* | | Module | SRAMb | Module | |
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* | | |--------+--->| | |
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* | +---------+ | +--------+ |
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* | v |
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* +-----------------------------------------------+
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* formal_port_sramb
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*
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*******************************************************************/
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@ -55,4 +55,14 @@ void add_primitive_pb_type_module_nets(ModuleManager& module_manager,
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const size_t& child_instance_id,
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const CircuitLibrary& circuit_lib,
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t_pb_type* cur_pb_type);
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void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const ModuleId& logic_module,
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const size_t& logic_instance_id,
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const ModuleId& memory_module,
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const size_t& memory_instance_id,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& logic_model);
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#endif
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@ -156,11 +156,26 @@ void print_verilog_primitive_block(std::fstream& fp,
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/* Add nets to connect the logic model ports to pb_type ports */
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add_primitive_pb_type_module_nets(module_manager, primitive_module, logic_module, logic_instance_id, circuit_lib, primitive_pb_graph_node->pb_type);
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/* TODO: add the associated memory module as a child of primitive module */
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/* Add the associated memory module as a child of primitive module */
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std::string memory_module_name = generate_memory_module_name(circuit_lib, primitive_model, sram_model, std::string(verilog_mem_posfix));
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ModuleId memory_module = module_manager.find_module(memory_module_name);
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/* TODO: Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */
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/* If there is no memory module required, we can skip the assocated net addition */
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if (ModuleId::INVALID() != memory_module) {
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size_t memory_instance_id = module_manager.num_instance(primitive_module, memory_module);
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/* Add the memory module as a child of primitive module */
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module_manager.add_child_module(primitive_module, memory_module);
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/* TODO: write the verilog module */
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/* Add nets to connect regular and mode-select SRAM ports to the SRAM port of memory module */
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add_module_nets_between_logic_and_memory_sram_bus(module_manager, primitive_module,
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logic_module, logic_instance_id,
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memory_module, memory_instance_id,
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circuit_lib, primitive_model);
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/* TODO: Add nets to connect configuration ports from memory module to primitive module */
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/* TODO: Add nets to connect formal verification ports from memory module to primitive module */
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}
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/* Write the verilog module */
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write_verilog_module_to_file(fp, module_manager, primitive_module, use_explicit_mapping);
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/* Add an empty line as a splitter */
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