From 6630c17c237a49872d9180d01ff077770df3dda8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 14 Feb 2022 13:07:31 -0800 Subject: [PATCH] [Test] Use preconfigured testbench template to run counter8 tests --- .../tasks/benchmark_sweep/counter8/config/task.conf | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf index 33011ced2..9540535b0 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter8/config/task.conf @@ -16,12 +16,9 @@ timeout_each_job = 5*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -# VPR parameters -# # Use a fixed routing channel width to save runtime -vpr_route_chan_width=50 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml