refactoring Verilog simulation flag generations

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c

@@ -264,17 +264,16 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
   init_pb_types_num_iopads();
   /* init_grids_num_mode_bits(); */
 
-  /* TODO: This is the old function, which will be deprecated when refactoring is done */
+  /* Print Verilog files containing preprocessing flags */
-  /*
-  dump_verilog_defines_preproc(src_dir_path,
-                               vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
-   */
-
   print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
                                             vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
 
+  print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
+                                               vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
+  /*
   dump_verilog_simulation_preproc(src_dir_path,
                                vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
+   */
 
   /* Generate primitive Verilog modules, which are corner stones of FPGA fabric 
    * Note that this function MUST be called before Verilog generation of

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.cpp

@@ -153,3 +153,43 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
   fp.close();
 }
 
+/********************************************************************
+ * Print a Verilog file containing simulation-related preprocessing flags
+ *******************************************************************/
+void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
+                                                  const t_syn_verilog_opts& fpga_verilog_opts) {
+
+  std::string verilog_fname = src_dir + std::string(defines_verilog_simulation_file_name);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_handler(fp);
+
+  /* Print the title */
+  print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); 
+
+  /* To enable manualy checked simulation */
+  if (TRUE == fpga_verilog_opts.print_top_testbench) {
+    print_verilog_define_flag(fp, std::string(initial_simulation_flag), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable auto-checked simulation */
+  if (TRUE == fpga_verilog_opts.print_autocheck_top_testbench) {
+    print_verilog_define_flag(fp, std::string(autochecked_simulation_flag), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable pre-configured FPGA simulation */
+  if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) {
+    print_verilog_define_flag(fp, std::string(formal_simulation_flag), 1);
+    fp << std::endl;
+  } 
+
+
+  /* Close the file stream */
+  fp.close();
+}

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_auxiliary_netlists.h

@@ -13,4 +13,7 @@ void print_include_netlists(const std::string& src_dir,
 void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
                                                const t_syn_verilog_opts& fpga_verilog_opts);
 
+void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
+                                                  const t_syn_verilog_opts& fpga_verilog_opts);
+
 #endif 

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c

@@ -164,45 +164,6 @@ void dump_verilog_file_header(FILE* fp,
   return;
 }
 
-/* Dump preproc */
-void dump_verilog_preproc(FILE* fp, 
-                          t_syn_verilog_opts fpga_verilog_opts,
-                          enum e_verilog_tb_type verilog_tb_type) {
-
-  if (NULL == fp) {
-    vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s, LINE[%d]) FileHandle is NULL!\n",__FILE__,__LINE__); 
-    exit(1);
-  } 
-
-  /* To enable timing */
-  if (TRUE == fpga_verilog_opts.include_timing) {
-    fprintf(fp, "`define %s 1\n", verilog_timing_preproc_flag);
-    fprintf(fp, "\n");
-  } 
-
-  /* To enable timing */
-  if (TRUE == fpga_verilog_opts.include_signal_init) {
-    fprintf(fp, "`define %s 1\n", verilog_signal_init_preproc_flag);
-    fprintf(fp, "\n");
-  } 
-
-  /* To enable formal verfication flag */
-  if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) {
-    fprintf(fp, "`define %s 1\n",
-                 verilog_formal_verification_preproc_flag); // the flag to enable formal verification during compilation
-    fprintf(fp, "\n");
-  } 
-
-  /* To enable functional verfication with Icarus */
-  if (TRUE == fpga_verilog_opts.include_icarus_simulator) {
-    fprintf(fp, "`define %s 1\n",
-                 icarus_simulator_flag); // the flag to enable formal verification during compilation
-    fprintf(fp, "\n");
-  } 
-
-  return;
-}
-
 void dump_simulation_preproc(FILE* fp, 
                              t_syn_verilog_opts fpga_verilog_opts,
                              enum e_verilog_tb_type verilog_tb_type) {
@@ -268,41 +229,6 @@ void dump_verilog_simulation_preproc(char* subckt_dir,
   return;
 }
 
-void dump_verilog_defines_preproc(char* subckt_dir,
-                                 t_syn_verilog_opts fpga_verilog_opts) {
-  /* Create a file handler */
-  FILE* fp = NULL;
-  char* file_description = NULL;
-  char* fname = NULL;
-
-  fname = my_strcat(subckt_dir, 
-                    defines_verilog_file_name);
-
-  /* Create a file*/
-  fp = fopen(fname, "w");
-
-  if (NULL == fp) {
-    vpr_printf(TIO_MESSAGE_ERROR,
-               "(FILE:%s,LINE[%d]) Failure in create Verilog netlist %s",
-               __FILE__, __LINE__, fname); 
-    exit(1);
-  } 
-
-  /* Generate the descriptions*/
-  file_description = "Preproc Flags";
-  dump_verilog_file_header(fp, file_description);
-
-  /* Dump the defines preproc flags*/
-  dump_verilog_preproc(fp, fpga_verilog_opts, VERILOG_TB_TOP); 
-
-  fclose(fp);
-
-  /* Free */
-  my_free(fname);
-
-  return;
-}
-
 void verilog_include_defines_preproc_file(FILE* fp, 
                                           char* verilog_dir) {
   char* temp_include_file_path = NULL;

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h

@@ -22,9 +22,6 @@ void dump_simulation_preproc(FILE* fp,
 void dump_verilog_simulation_preproc(char* subckt_dir,
                                      t_syn_verilog_opts fpga_verilog_opts);
 
-void dump_verilog_defines_preproc(char* subckt_dir,
-                                 t_syn_verilog_opts fpga_verilog_opts);
-
 void verilog_include_simulation_defines_file(FILE* fp, 
                                              char* formatted_verilog_dir);