riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

bug fixing for frame-based configuration protocol and rename some naming function to be generic

This commit is contained in:
tangxifan 2020-05-28 12:25:47 -06:00
parent 3a0d3b4e95
commit 65df309419
13 changed files with 90 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
View File

@ -135,9 +135,11 @@ size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_
size_t num_err = 0;
if (port_size_to_check != circuit_lib.port_size(circuit_port)) {
VTR_LOG_ERROR(circuit_lib.model_name(circuit_model).c_str(),
VTR_LOG_ERROR("Expect circuit model %s to have %d %s ports but only see %d!\n",
circuit_lib.model_name(circuit_model).c_str(),
port_size_to_check,
CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_port))],
port_size_to_check);
circuit_lib.port_size(circuit_port));
/* Incremental the counter for errors */
num_err++;
}
@ -282,7 +284,7 @@ size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib,
/* Check if we has 1 output with size 2 */
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
CIRCUIT_MODEL_PORT_OUTPUT,
2, 2, false);
2, 1, false);
/* basic check finished here */
if (false == check_blwl) {
return num_err;

8
openfpga/src/base/openfpga_naming.cpp
View File

@ -687,18 +687,18 @@ std::string generate_configuration_chain_tail_name() {
}
/*********************************************************************
* Generate the memory output port name of a configuration chain
* Generate the memory output port name of a configurable memory
* TODO: This could be replaced as a constexpr string
*********************************************************************/
std::string generate_configuration_chain_data_out_name() {
std::string generate_configurable_memory_data_out_name() {
return std::string("mem_out");
}
/*********************************************************************
* Generate the inverted memory output port name of a configuration chain
* Generate the inverted memory output port name of a configurable memory
* TODO: This could be replaced as a constexpr string
*********************************************************************/
std::string generate_configuration_chain_inverted_data_out_name() {
std::string generate_configurable_memory_inverted_data_out_name() {
return std::string("mem_outb");
}

4
openfpga/src/base/openfpga_naming.h
View File

@ -168,9 +168,9 @@ std::string generate_configuration_chain_head_name();
std::string generate_configuration_chain_tail_name();
std::string generate_configuration_chain_data_out_name();
std::string generate_configurable_memory_data_out_name();
std::string generate_configuration_chain_inverted_data_out_name();
std::string generate_configurable_memory_inverted_data_out_name();
std::string generate_mux_local_decoder_addr_port_name();

11
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -414,7 +414,8 @@ void add_module_pb_graph_pin2pin_net(ModuleManager& module_manager,
module_manager.add_module_net_sink(pb_module, pin2pin_net, pin_pb_type_module, pin_pb_type_instance, pin_module_port_id, pin_module_pin_id);
break;
default:
VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid pin-to-pin interconnection type!\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid pin-to-pin interconnection type!\n");
exit(1);
}
}
@ -598,8 +599,9 @@ void add_module_pb_graph_pin_interc(ModuleManager& module_manager,
break;
}
default:
VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid interconnection type for %s [at Architecture XML LINE%d]!\n",
cur_interc->name, cur_interc->line_num);
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid interconnection type for %s [at Architecture XML LINE%d]!\n",
cur_interc->name, cur_interc->line_num);
exit(1);
}
}
@ -686,7 +688,8 @@ void add_module_pb_graph_port_interc(ModuleManager& module_manager,
break;
}
default:
VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid pb port type!\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid pb port type!\n");
exit(1);
}
}

44
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -396,10 +396,10 @@ void build_memory_chain_module(ModuleManager& module_manager,
for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
std::string port_name;
if (0 == iport) {
port_name = generate_configuration_chain_data_out_name();
port_name = generate_configurable_memory_data_out_name();
} else {
VTR_ASSERT( 1 == iport);
port_name = generate_configuration_chain_inverted_data_out_name();
port_name = generate_configurable_memory_inverted_data_out_name();
}
BasicPort output_port(port_name, num_mems);
module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
@ -421,10 +421,10 @@ void build_memory_chain_module(ModuleManager& module_manager,
for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
std::string port_name;
if (0 == iport) {
port_name = generate_configuration_chain_data_out_name();
port_name = generate_configurable_memory_data_out_name();
} else {
VTR_ASSERT( 1 == iport);
port_name = generate_configuration_chain_inverted_data_out_name();
port_name = generate_configurable_memory_inverted_data_out_name();
}
std::vector<ModuleNetId> output_nets = add_module_output_nets_to_chain_mem_modules(module_manager, mem_module,
port_name, circuit_lib, sram_output_ports[iport],
@ -657,12 +657,22 @@ void build_frame_memory_module(ModuleManager& module_manager,
ModulePortId mem_addr_port = module_manager.add_port(mem_module, addr_port, ModuleManager::MODULE_INPUT_PORT);
/* Input: Data port */
BasicPort data_port(std::string(DECODER_DATA_IN_PORT_NAME), data_size);
BasicPort data_port(std::string(DECODER_DATA_IN_PORT_NAME), 1);
ModulePortId mem_data_port = module_manager.add_port(mem_module, data_port, ModuleManager::MODULE_INPUT_PORT);
/* Should have only 1 or 2 output port */
VTR_ASSERT( (1 == sram_output_ports.size()) || ( 2 == sram_output_ports.size()) );
/* Add each output port: port width should match the number of memories */
for (const auto& port : sram_output_ports) {
BasicPort output_port(circuit_lib.port_prefix(port), num_mems * circuit_lib.port_size(port));
for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
std::string port_name;
if (0 == iport) {
port_name = generate_configurable_memory_data_out_name();
} else {
VTR_ASSERT( 1 == iport);
port_name = generate_configurable_memory_inverted_data_out_name();
}
BasicPort output_port(port_name, num_mems);
module_manager.add_port(mem_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
}
@ -717,7 +727,19 @@ void build_frame_memory_module(ModuleManager& module_manager,
}
/* Wire inputs of parent module to outputs of child modules */
add_module_output_nets_to_mem_modules(module_manager, mem_module, circuit_lib, sram_output_ports, sram_mem_module, i, sram_instance);
for (size_t iport = 0; iport < sram_output_ports.size(); ++iport) {
std::string port_name;
if (0 == iport) {
port_name = generate_configurable_memory_data_out_name();
} else {
VTR_ASSERT( 1 == iport);
port_name = generate_configurable_memory_inverted_data_out_name();
}
add_module_output_nets_to_chain_mem_modules(module_manager, mem_module,
port_name, circuit_lib, sram_output_ports[iport],
sram_mem_module, i, sram_instance);
}
}
/* Add global ports to the pb_module:
@ -727,7 +749,6 @@ void build_frame_memory_module(ModuleManager& module_manager,
add_module_global_ports_from_child_modules(module_manager, mem_module);
}
/*********************************************************************
* Generate Verilog modules for the memories that are used
* by a circuit model
@ -818,8 +839,9 @@ void build_mux_memory_module(ModuleManager& module_manager,
*/
break;
default:
VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid design technology of multiplexer '%s'\n",
circuit_lib.model_name(mux_model).c_str());
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid design technology of multiplexer '%s'\n",
circuit_lib.model_name(mux_model).c_str());
exit(1);
}
}

2
openfpga/src/fpga_bitstream/arch_bitstream_writer.cpp
View File

@ -85,7 +85,7 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp,
fp << "\t<bitstream>" << std::endl;
for (const ConfigBitId& child_bit : bitstream_manager.block_bits(block)) {
fp << "\t\t<bit";
fp << " memory_port=\"" << generate_configuration_chain_data_out_name() << "[" << bit_counter << "]" << "\"";
fp << " memory_port=\"" << generate_configurable_memory_data_out_name() << "[" << bit_counter << "]" << "\"";
fp << " value=\"" << bitstream_manager.bit_value(child_bit) << "\"";
fp << "/>" << std::endl;
bit_counter++;

6
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -98,7 +98,7 @@ void build_primitive_bitstream(BitstreamManager& bitstream_manager,
std::string mem_block_name = generate_memory_module_name(circuit_lib, primitive_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX));
ModuleId mem_module = module_manager.find_module(mem_block_name);
VTR_ASSERT (true == module_manager.valid_module_id(mem_module));
ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name());
ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configurable_memory_data_out_name());
VTR_ASSERT(mode_select_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width());
/* Create a block for the bitstream which corresponds to the memory module associated to the LUT */
@ -194,7 +194,7 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag
std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX));
ModuleId mux_mem_module = module_manager.find_module(mem_module_name);
VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configurable_memory_data_out_name());
VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
/* Add the bistream to the bitstream manager */
@ -424,7 +424,7 @@ void build_lut_bitstream(BitstreamManager& bitstream_manager,
std::string mem_block_name = generate_memory_module_name(circuit_lib, lut_model, sram_models[0], std::string(MEMORY_MODULE_POSTFIX));
ModuleId mem_module = module_manager.find_module(mem_block_name);
VTR_ASSERT (true == module_manager.valid_module_id(mem_module));
ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configuration_chain_data_out_name());
ModulePortId mem_out_port_id = module_manager.find_module_port(mem_module, generate_configurable_memory_data_out_name());
VTR_ASSERT(lut_bitstream.size() == module_manager.module_port(mem_module, mem_out_port_id).get_width());
/* Create a block for the bitstream which corresponds to the memory module associated to the LUT */

4
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -76,7 +76,7 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX));
ModuleId mux_mem_module = module_manager.find_module(mem_module_name);
VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configurable_memory_data_out_name());
VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
/* Add the bistream to the bitstream manager */
@ -230,7 +230,7 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX));
ModuleId mux_mem_module = module_manager.find_module(mem_module_name);
VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configurable_memory_data_out_name());
VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
/* Add the bistream to the bitstream manager */

8
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -206,7 +206,7 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp,
bit_hierarchy_path += std::string(".");
/* Find the bit index in the parent block */
BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(),
BasicPort config_data_port(bit_hierarchy_path + generate_configurable_memory_data_out_name(),
bitstream_manager.block_bits(config_block_id).size());
/* Wire it to the configuration bit: access both data out and data outb ports */
@ -239,7 +239,7 @@ void print_verilog_preconfig_top_module_assign_bitstream(std::fstream& fp,
bit_hierarchy_path += std::string(".");
/* Find the bit index in the parent block */
BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(),
BasicPort config_datab_port(bit_hierarchy_path + generate_configurable_memory_inverted_data_out_name(),
bitstream_manager.block_bits(config_block_id).size());
std::vector<size_t> config_datab_values;
@ -290,10 +290,10 @@ void print_verilog_preconfig_top_module_deposit_bitstream(std::fstream& fp,
bit_hierarchy_path += std::string(".");
/* Find the bit index in the parent block */
BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(),
BasicPort config_data_port(bit_hierarchy_path + generate_configurable_memory_data_out_name(),
bitstream_manager.block_bits(config_block_id).size());
BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(),
BasicPort config_datab_port(bit_hierarchy_path + generate_configurable_memory_inverted_data_out_name(),
bitstream_manager.block_bits(config_block_id).size());
/* Wire it to the configuration bit: access both data out and data outb ports */

3
openfpga/src/utils/circuit_library_utils.cpp
View File

@ -143,7 +143,8 @@ size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, sram_orgz_type));
break;
default:
VTR_LOG_ERROR("Invalid design technology for SRAM model!\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid design technology for SRAM model!\n");
exit(1);
}
}

19
openfpga/src/utils/memory_utils.cpp
View File

@ -70,8 +70,8 @@ std::map<std::string, BasicPort> generate_cmos_mem_module_port2port_map(const Ba
/* Link the SRAM output ports of the memory module */
VTR_ASSERT( 2 == mem_output_bus_ports.size() );
port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0];
port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1];
port2port_name_map[generate_configurable_memory_data_out_name()] = mem_output_bus_ports[0];
port2port_name_map[generate_configurable_memory_inverted_data_out_name()] = mem_output_bus_ports[1];
break;
}
case CONFIG_MEM_MEMORY_BANK:
@ -127,15 +127,16 @@ std::map<std::string, BasicPort> generate_rram_mem_module_port2port_map(const Ba
/* Link the SRAM output ports of the memory module */
VTR_ASSERT( 2 == mem_output_bus_ports.size() );
port2port_name_map[generate_configuration_chain_data_out_name()] = mem_output_bus_ports[0];
port2port_name_map[generate_configuration_chain_inverted_data_out_name()] = mem_output_bus_ports[1];
port2port_name_map[generate_configurable_memory_data_out_name()] = mem_output_bus_ports[0];
port2port_name_map[generate_configurable_memory_inverted_data_out_name()] = mem_output_bus_ports[1];
break;
}
case CONFIG_MEM_MEMORY_BANK:
/* TODO: link BL/WL/Reserved Ports to the inputs of a memory module */
break;
default:
VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid type of SRAM organization!\n");
exit(1);
}
@ -342,7 +343,8 @@ std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_
break;
}
default:
VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid type of SRAM organization !\n");
exit(1);
}
@ -378,8 +380,11 @@ size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type,
break;
case CONFIG_MEM_MEMORY_BANK:
break;
case CONFIG_MEM_FRAME_BASED:
break;
default:
VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid type of SRAM organization!\n");
exit(1);
}

21
openfpga/src/utils/module_manager_utils.cpp
View File

@ -234,7 +234,8 @@ void add_sram_ports_to_module_manager(ModuleManager& module_manager,
break;
}
default:
VTR_LOG_ERROR("Invalid type of SRAM organization !\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid type of SRAM organization !\n");
exit(1);
}
}
@ -613,8 +614,8 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
}
/* Get the SRAM port name of memory model */
/* TODO: this should be a constant expression and it should be the same for all the memory module! */
std::string memory_model_sram_port_name = generate_configuration_chain_data_out_name();
/* This should be a constant expression and it should be the same for all the memory module! */
std::string memory_model_sram_port_name = generate_configurable_memory_data_out_name();
/* Find the corresponding ports in memory module */
ModulePortId mem_module_sram_port_id = module_manager.find_module_port(memory_module, memory_model_sram_port_name);
@ -649,7 +650,7 @@ void add_module_nets_between_logic_and_memory_sram_bus(ModuleManager& module_man
}
/* Get the SRAM port name of memory model */
std::string memory_model_sramb_port_name = generate_configuration_chain_inverted_data_out_name();
std::string memory_model_sramb_port_name = generate_configurable_memory_inverted_data_out_name();
/* Find the corresponding ports in memory module */
ModulePortId mem_module_sramb_port_id = module_manager.find_module_port(memory_module, memory_model_sramb_port_name);
@ -1099,7 +1100,8 @@ void add_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
add_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module);
break;
default:
VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid type of SRAM organization!\n");
exit(1);
}
}
@ -1174,7 +1176,8 @@ void add_module_nets_memory_config_bus(ModuleManager& module_manager,
/* TODO: */
break;
default:
VTR_LOG_ERROR("Invalid type of memory design technology !\n");
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Invalid type of memory design technology!\n");
exit(1);
}
}
@ -1593,7 +1596,11 @@ void add_module_bus_nets(ModuleManager& module_manager,
if (src_port.get_width() != des_port.get_width()) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Unmatched port size: src_port is %lu while des_port is %lu!\n");
"Unmatched port size: src_port %s is %lu while des_port %s is %lu!\n",
src_port.get_name().c_str(),
src_port.get_width(),
des_port.get_name().c_str(),
des_port.get_width());
exit(1);
}

1
openfpga/src/utils/mux_utils.cpp
View File

@ -260,6 +260,7 @@ size_t find_cmos_mux_num_config_bits(const CircuitLibrary& circuit_lib,
case CONFIG_MEM_MEMORY_BANK:
case CONFIG_MEM_SCAN_CHAIN:
case CONFIG_MEM_STANDALONE:
case CONFIG_MEM_FRAME_BASED:
num_config_bits = mux_graph.num_memory_bits();
break;
default: