add simulation ini file writer

openfpga/CMakeLists.txt

@@ -22,6 +22,7 @@ target_link_libraries(libopenfpga
                       libarchopenfpga
                       libopenfpgashell
                       libopenfpgautil
+                      libini
                       libvtrutil
                       libvpr8)
 

openfpga/src/fpga_verilog/simulation_info_writer.cpp

@@ -0,0 +1,67 @@
+/*********************************************************************
+ * This function includes the writer for generating exchangeable
+ * information, in order to interface different simulators   
+ ********************************************************************/
+#include <cmath>
+#include <ctime>
+#include <map>
+#define MINI_CASE_SENSITIVE
+#include "ini.h"
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+
+#include "simulation_utils.h"
+
+#include "verilog_constants.h"
+#include "simulation_info_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Top-level function to write an ini file which contains exchangeable
+ * information, in order to interface different Verilog simulators
+ ********************************************************************/
+void print_verilog_simulation_info(const std::string& ini_fname,
+                                   const std::string& circuit_name,
+                                   const std::string& src_dir,
+                                   const size_t& num_program_clock_cycles,
+                                   const int& num_operating_clock_cycles,
+                                   const float& prog_clock_freq,
+                                   const float& op_clock_freq) {
+
+  std::string timer_message = std::string("Write exchangeable file containing simulation information '") + ini_fname + std::string("'");
+
+  /* Start time count */
+  vtr::ScopedStartFinishTimer timer(timer_message);
+
+  /* Use default name if user does not provide one */
+  VTR_ASSERT(true != ini_fname.empty());
+
+  mINI::INIStructure ini;
+  // std::map<char, int> units_map;
+  // units_map['s']=1;  // units_map['ms']=1E-3;  // units_map['us']=1E-6;
+  // units_map['ns']=1E-9;  // units_map['ps']=1E-12;  // units_map['fs']=1E-15;
+
+  /* Compute simulation time period */
+  float simulation_time_period = find_simulation_time_period(1E-3,
+                                                             num_program_clock_cycles,
+                                                             1. / prog_clock_freq,
+                                                             num_operating_clock_cycles,
+                                                             1. / op_clock_freq);
+  ini["SIMULATION_DECK"]["PROJECTNAME "] = "ModelSimProject";
+  ini["SIMULATION_DECK"]["BENCHMARK "] = circuit_name;
+  ini["SIMULATION_DECK"]["TOP_TB"] = circuit_name + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX);
+  ini["SIMULATION_DECK"]["SIMTIME "] = std::to_string(simulation_time_period);
+  ini["SIMULATION_DECK"]["UNIT "] = "ms";
+  ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
+  ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME);
+  ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX));
+
+  mINI::INIFile file(ini_fname);
+  file.generate(ini, true);
+}
+
+} /* end namespace openfpga */

openfpga/src/fpga_verilog/simulation_info_writer.h

@@ -0,0 +1,26 @@
+#ifndef SIMULATION_INFO_WRITER_H
+#define SIMULATION_INFO_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_simulation_info(const std::string& ini_fname,
+                                   const std::string& circuit_name,
+                                   const std::string& src_dir,
+                                   const size_t& num_program_clock_cycles,
+                                   const int& num_operating_clock_cycles,
+                                   const float& prog_clock_freq,
+                                   const float& op_clock_freq);
+
+} /* end namespace openfpga */
+
+#endif

openfpga/src/fpga_verilog/verilog_api.cpp

@@ -23,6 +23,7 @@
 #include "verilog_preconfig_top_module.h"
 #include "verilog_formal_random_top_testbench.h"
 #include "verilog_top_testbench.h"
+#include "simulation_info_writer.h"
 
 /* Header file for this source file */
 #include "verilog_api.h"
@@ -204,22 +205,18 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                                 simulation_setting);
   }
  
-  /* TODO: Generate exchangeable files which contains simulation settings 
+  /* Generate exchangeable files which contains simulation settings */
   if (true == options.print_simulation_ini()) {
-    std::string simulation_ini_file_name;
+    std::string simulation_ini_file_name = options.simulation_ini_path();
-    if (true != options.simulation_ini_path()) {
+    VTR_ASSERT(true != options.simulation_ini_path().empty());
-      simulation_ini_file_name = options.simulation_ini_path();
-    }
     print_verilog_simulation_info(simulation_ini_file_name,
-                                  format_dir_path(chomped_parent_dir),
                                   netlist_name,
                                   src_dir_path,
                                   bitstream_manager.bits().size(),
-                                  simulation_setting.num_clock_cycle(),
+                                  simulation_setting.num_clock_cycles(),
                                   simulation_setting.programming_clock_frequency(),
                                   simulation_setting.operating_clock_frequency());
   }
-  */
 
   /* Generate a Verilog file including all the netlists that have been generated */
   print_include_netlists(src_dir_path,

openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp

@@ -23,7 +23,6 @@ namespace openfpga {
 /********************************************************************
  * Local constant variables
  *******************************************************************/
-constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
 
 /********************************************************************
  * Print a file that includes all the netlists that have been generated

openfpga/src/fpga_verilog/verilog_constants.h

@@ -22,6 +22,7 @@ constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
 constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
 // End of Icarus variables and flag
 
+constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
 constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
 constexpr char* FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX = "_top_formal_verification.v"; 
 constexpr char* TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_top_tb.v"; /* !!! must be consist with the modelsim_testbench_module_postfix */ 
@@ -52,6 +53,8 @@ constexpr char* FORMAL_VERIFICATION_TOP_MODULE_POSTFIX = "_top_formal_verificati
 constexpr char* FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX = "_fm";
 constexpr char* FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME = "U0_formal_verification";
 
+constexpr char* FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX = "_top_formal_verification_random_tb";
+
 #define VERILOG_DEFAULT_SIGNAL_INIT_VALUE 0
 
 #endif

openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp

@@ -31,7 +31,6 @@ namespace openfpga {
 /********************************************************************
  * Local variables used only in this file
  *******************************************************************/
-constexpr char* FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX = "_top_formal_verification_random_tb";
 constexpr char* FPGA_PORT_POSTFIX = "_gfpga";
 constexpr char* BENCHMARK_PORT_POSTFIX = "_bench";
 constexpr char* CHECKFLAG_PORT_POSTFIX = "_flag";

openfpga/test_script/s298_k6_frac.openfpga

@@ -38,7 +38,7 @@ fpga_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepene
 write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
 
 # Write the Verilog testbench for FPGA fabric
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench
+write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src --reference_benchmark_file_path /var/tmp/xtang/s298.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
 
 # Finish and exit OpenFPGA
 exit