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[Tool] Bug fix in the global tile connection by considering all the subtiles

This commit is contained in:
tangxifan 2021-01-10 11:52:38 -07:00
parent e58e1e86c2
commit 65b2fe3ab7
1 changed files with 31 additions and 27 deletions
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16
openfpga/src/fabric/build_top_module_connection.cpp
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@ -709,7 +709,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
t_physical_tile_type_ptr physical_tile = grids[grid_coordinate.x()][grid_coordinate.y()].type;
/* Find the port of the grid module according to the tile annotation */
int grid_pin_index = physical_tile->num_pins;
int grid_pin_start_index = physical_tile->num_pins;
for (const t_physical_tile_port& tile_port : physical_tile->ports) {
if (std::string(tile_port.name) == tile_port_to_connect.get_name()) {
BasicPort ref_tile_port(tile_port.name, tile_port.num_pins);
@ -725,12 +725,12 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
ref_tile_port.get_msb());
return CMD_EXEC_FATAL_ERROR;
}
grid_pin_index = tile_port.absolute_first_pin_index;
grid_pin_start_index = tile_port.absolute_first_pin_index;
break;
}
}
/* Ensure the pin index is valid */
VTR_ASSERT(grid_pin_index < physical_tile->num_pins);
VTR_ASSERT(grid_pin_start_index < physical_tile->num_pins);
/* Find the module name for this type of grid */
std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
@ -739,6 +739,12 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
size_t grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()];
VTR_ASSERT(1 == physical_tile->equivalent_sites.size());
/* A tile may consist of multiple subtile, connect to all the pins from sub tiles */
for (int iz = 0; iz < physical_tile->capacity; ++iz) {
/* TODO: This should be replaced by using a pin mapping data structure from physical tile! */
int grid_pin_index = grid_pin_start_index + iz * physical_tile->equivalent_sites[0]->pb_type->num_pins;
/* Find the module pin */
size_t grid_pin_width = physical_tile->pin_width_offset[grid_pin_index];
size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index];
@ -752,9 +758,6 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_port_id));
/* Build nets */
add_module_bus_nets(module_manager, top_module,
top_module, 0, top_module_port,
grid_module, grid_instance, grid_port_id);
BasicPort src_port = module_manager.module_port(top_module, top_module_port);
for (size_t pin_id = 0; pin_id < tile_port_to_connect.pins().size(); ++pin_id) {
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
@ -766,6 +769,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
module_manager.add_module_net_sink(top_module, net, grid_module, grid_instance, grid_port_id, tile_port_to_connect.pins()[pin_id]);
}
}
}
return CMD_EXEC_SUCCESS;
}