From 65995d7c13da678269c1608551368193dbe5a889 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 27 Jul 2023 17:03:02 -0700 Subject: [PATCH] [test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules --- ...reconfig_testbench_example_script.openfpga | 5 +- .../hetero_fabric_tile/config/task.conf | 54 +++++++++++++++++++ .../hetero_fabric_tile/config/tile_config.xml | 1 + .../config/task.conf | 2 + .../config/task.conf | 2 + .../config/task.conf | 2 + .../config/task.conf | 2 + .../config/task.conf | 4 +- 8 files changed, 70 insertions(+), 2 deletions(-) create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/hetero_fabric_tile/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/hetero_fabric_tile/config/tile_config.xml diff --git a/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga index 3fb1b3d5f..0e80a226a 100644 --- a/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,6 +15,9 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/hetero_fabric_tile/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/hetero_fabric_tile/config/task.conf new file mode 100644 index 000000000..29fc6d6d1 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/hetero_fabric_tile/config/task.conf @@ -0,0 +1,54 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on +openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose +openfpga_vpr_device=3x2 +openfpga_vpr_route_chan_width=40 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v +bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v +bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = mac_2 +bench1_top = mac_4 +bench2_top = mac_6 +bench3_top = mac_8 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/hetero_fabric_tile/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/hetero_fabric_tile/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/tile_organization/hetero_fabric_tile/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig/config/task.conf index 62df599ae..127d9efc7 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig/config/task.conf @@ -19,6 +19,8 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= openfpga_vpr_device=2x2 openfpga_vpr_route_chan_width=20 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig/config/task.conf index 48fedfa6d..38f1c7114 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig/config/task.conf @@ -19,6 +19,8 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= openfpga_vpr_device=4x4 openfpga_vpr_route_chan_width=20 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/task.conf index e2e89a59b..9268b12bc 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_adder_chain/config/task.conf @@ -19,6 +19,8 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= openfpga_vpr_device=auto openfpga_vpr_route_chan_width=40 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_global_tile_clock/config/task.conf index 240cdc6d4..11708b954 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_global_tile_clock/config/task.conf @@ -19,6 +19,8 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= openfpga_vpr_device=auto openfpga_vpr_route_chan_width=20 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_preconfig/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_preconfig/config/task.conf index d1164b236..2c397c1ac 100644 --- a/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_preconfig/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_preconfig/config/task.conf @@ -18,7 +18,9 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= openfpga_vpr_device=auto openfpga_vpr_route_chan_width=20 openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml