From 653d7d5aa1dd58205eea8d96a70a69a6c565ffbb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 1 Feb 2020 11:49:39 -0700 Subject: [PATCH] placer compilation errors elimated for RRGraph deployment --- vpr/src/base/vpr_context.h | 1 + vpr/src/device/rr_graph_obj_util.cpp | 65 +++++++++ vpr/src/device/rr_graph_obj_util.h | 21 +++ vpr/src/device/rr_graph_types.h | 3 + vpr/src/device/rr_graph_util.cpp | 30 ----- vpr/src/device/rr_graph_util.h | 15 --- vpr/src/device/write_xml_rr_graph_obj.cpp | 2 - vpr/src/draw/draw.cpp | 153 +++++++++++----------- vpr/src/draw/draw.h | 4 +- vpr/src/draw/search_bar.cpp | 18 +-- vpr/src/draw/search_bar.h | 4 +- vpr/src/place/timing_place_lookup.cpp | 42 +++--- vpr/src/route/route_common.cpp | 14 +- vpr/src/route/route_export.h | 4 +- vpr/src/route/rr_graph.cpp | 44 +++---- vpr/src/route/rr_graph.h | 2 +- 16 files changed, 230 insertions(+), 192 deletions(-) create mode 100644 vpr/src/device/rr_graph_obj_util.cpp create mode 100644 vpr/src/device/rr_graph_obj_util.h delete mode 100644 vpr/src/device/rr_graph_util.cpp delete mode 100644 vpr/src/device/rr_graph_util.h diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 7f4ba43dc..9a59e89c8 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -286,6 +286,7 @@ struct RoutingContext : public Context { vtr::vector trace; vtr::vector> trace_nodes; + /* Xifan Tang: this should adopt RRNodeId as well */ vtr::vector> net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */ vtr::vector> rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */ diff --git a/vpr/src/device/rr_graph_obj_util.cpp b/vpr/src/device/rr_graph_obj_util.cpp new file mode 100644 index 000000000..92d27e083 --- /dev/null +++ b/vpr/src/device/rr_graph_obj_util.cpp @@ -0,0 +1,65 @@ +/**************************************************************************** + * This file include most-utilized functions that manipulate on the + * RRGraph object + ***************************************************************************/ +#include "rr_graph_obj.h" +#include "rr_graph_obj_util.h" + +/**************************************************************************** + * Find the switches interconnecting two nodes + * Return a vector of switch ids + ***************************************************************************/ +std::vector find_rr_graph_switches(const RRGraph& rr_graph, + const RRNodeId& from_node, + const RRNodeId& to_node) { + std::vector switches; + std::vector edges = rr_graph.find_edges(from_node, to_node); + if (true == edges.empty()) { + /* edge is open, we return an empty vector of switches */ + return switches; + } + + /* Reach here, edge list is not empty, find switch id one by one + * and update the switch list + */ + for (auto edge : edges) { + switches.push_back(rr_graph.edge_switch(edge)); + } + + return switches; +} + +/********************************************************************* + * Like the RRGraph.find_node() but returns all matching nodes, + * rather than just the first. This is particularly useful for getting all instances + * of a specific IPIN/OPIN at a specific gird tile (x,y) location. + **********************************************************************/ +std::vector find_rr_graph_nodes(const RRGraph& rr_graph, + const int& x, + const int& y, + const t_rr_type& rr_type, + const int& ptc) { + std::vector indices; + + if (rr_type == IPIN || rr_type == OPIN) { + //For pins we need to look at all the sides of the current grid tile + + for (e_side side : SIDES) { + RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, ptc, side); + + if (rr_node_index != RRNodeId::INVALID()) { + indices.push_back(rr_node_index); + } + } + } else { + //Sides do not effect non-pins so there should only be one per ptc + RRNodeId rr_node_index = rr_graph.find_node(x, y, rr_type, ptc); + + if (rr_node_index != RRNodeId::INVALID()) { + indices.push_back(rr_node_index); + } + } + + return indices; +} + diff --git a/vpr/src/device/rr_graph_obj_util.h b/vpr/src/device/rr_graph_obj_util.h new file mode 100644 index 000000000..9a089d68c --- /dev/null +++ b/vpr/src/device/rr_graph_obj_util.h @@ -0,0 +1,21 @@ +#ifndef RR_GRAPH_OBJ_UTIL_H +#define RR_GRAPH_OBJ_UTIL_H + +/* Include header files which include data structures used by + * the function declaration + */ +#include +#include "rr_graph_obj.h" + +/* Get node-to-node switches in a RRGraph */ +std::vector find_rr_graph_switches(const RRGraph& rr_graph, + const RRNodeId& from_node, + const RRNodeId& to_node); + +std::vector find_rr_graph_nodes(const RRGraph& rr_graph, + const int& x, + const int& y, + const t_rr_type& rr_type, + const int& ptc); + +#endif diff --git a/vpr/src/device/rr_graph_types.h b/vpr/src/device/rr_graph_types.h index 51cf3a0dd..a4df4cd7f 100644 --- a/vpr/src/device/rr_graph_types.h +++ b/vpr/src/device/rr_graph_types.h @@ -19,6 +19,9 @@ enum e_direction : unsigned char { constexpr std::array DIRECTION_STRING = {{"INC_DIRECTION", "DEC_DIRECTION", "BI_DIRECTION", "NO_DIRECTION"}}; +/* Xifan Tang - string used in describe_rr_node() and write_xml_rr_graph_obj() */ +constexpr std::array DIRECTION_STRING_WRITE_XML = {{"INC_DIR", "DEC_DIR", "BI_DIR", "NO_DIR"}}; + /* Type of a routing resource node. x-directed channel segment, * * y-directed channel segment, input pin to a clb to pad, output * * from a clb or pad (i.e. output pin of a net) and: * diff --git a/vpr/src/device/rr_graph_util.cpp b/vpr/src/device/rr_graph_util.cpp deleted file mode 100644 index 495a66581..000000000 --- a/vpr/src/device/rr_graph_util.cpp +++ /dev/null @@ -1,30 +0,0 @@ -/**************************************************************************** - * This file include most-utilized functions that manipulate on the - * RRGraph object - ***************************************************************************/ -#include "rr_graph_util.h" -#include "rr_graph_obj.h" - -/**************************************************************************** - * Find the switches interconnecting two nodes - * Return a vector of switch ids - ***************************************************************************/ -std::vector find_rr_graph_switches(const RRGraph& rr_graph, - const RRNodeId& from_node, - const RRNodeId& to_node) { - std::vector switches; - std::vector edges = rr_graph.find_edges(from_node, to_node); - if (true == edges.empty()) { - /* edge is open, we return an empty vector of switches */ - return switches; - } - - /* Reach here, edge list is not empty, find switch id one by one - * and update the switch list - */ - for (auto edge : edges) { - switches.push_back(rr_graph.edge_switch(edge)); - } - - return switches; -} diff --git a/vpr/src/device/rr_graph_util.h b/vpr/src/device/rr_graph_util.h deleted file mode 100644 index 027356b86..000000000 --- a/vpr/src/device/rr_graph_util.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef RR_GRAPH_UTIL_H -#define RR_GRAPH_UTIL_H - -/* Include header files which include data structures used by - * the function declaration - */ -#include -#include "rr_graph_fwd.h" - -/* Get node-to-node switches in a RRGraph */ -std::vector find_rr_graph_switches(const RRGraph& rr_graph, - const RRNodeId& from_node, - const RRNodeId& to_node); - -#endif diff --git a/vpr/src/device/write_xml_rr_graph_obj.cpp b/vpr/src/device/write_xml_rr_graph_obj.cpp index a329b7bc0..8cd52938e 100644 --- a/vpr/src/device/write_xml_rr_graph_obj.cpp +++ b/vpr/src/device/write_xml_rr_graph_obj.cpp @@ -55,8 +55,6 @@ void write_rr_graph_node(fstream &fp, const RRGraph& rr_graph) { /* TODO: we should make it function full independent from device_ctx !!! */ auto& device_ctx = g_vpr_ctx.device(); - std::array DIRECTION_STRING_WRITE_XML = {{"INC_DIR", "DEC_DIR", "BI_DIR", "NO_DIR"}}; - fp << "\t" << endl; for (auto node : rr_graph.nodes()) { diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index a63e9c51c..03981194c 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -104,9 +104,9 @@ static void draw_chanx_to_chanx_edge(const RRNodeId& from_node, const RRNodeId& static void draw_chanx_to_chany_edge(const RRNodeId& chanx_node, int chanx_track, const RRNodeId& chany_node, int chany_track, enum e_edge_dir edge_dir, short switch_type, ezgl::renderer* g); static int get_track_num(const RRNodeId& inode, const vtr::OffsetMatrix& chanx_track, const vtr::OffsetMatrix& chany_track); static bool draw_if_net_highlighted(ClusterNetId inet); -static int draw_check_rr_node_hit(float click_x, float click_y); +static RRNodeId draw_check_rr_node_hit(float click_x, float click_y); -static void draw_expand_non_configurable_rr_nodes_recurr(int from_node, std::set& expanded_nodes); +static void draw_expand_non_configurable_rr_nodes_recurr(const RRNodeId& from_node, std::set& expanded_nodes); static bool highlight_rr_nodes(float x, float y); static void highlight_blocks(double x, double y); static void draw_reset_blk_colors(); @@ -119,9 +119,8 @@ static inline ezgl::rectangle draw_mux(ezgl::point2d origin, e_side orientation, static void draw_flyline_timing_edge(ezgl::point2d start, ezgl::point2d end, float incr_delay, ezgl::renderer* g); static void draw_routed_timing_edge(tatum::NodeId start_tnode, tatum::NodeId end_tnode, float incr_delay, ezgl::color color, ezgl::renderer* g); static void draw_routed_timing_edge_connection(tatum::NodeId src_tnode, tatum::NodeId sink_tnode, ezgl::color color, ezgl::renderer* g); -static std::vector trace_routed_connection_rr_nodes(const ClusterNetId net_id, const int driver_pin, const int sink_pin); -static bool trace_routed_connection_rr_nodes_recurr(const t_rt_node* rt_node, int sink_rr_node, std::vector& rr_nodes_on_path); -static t_edge_size find_edge(int prev_inode, int inode); +static std::vector trace_routed_connection_rr_nodes(const ClusterNetId net_id, const int driver_pin, const int sink_pin); +static bool trace_routed_connection_rr_nodes_recurr(const t_rt_node* rt_node, const RRNodeId& sink_rr_node, std::vector& rr_nodes_on_path); static void draw_color_map_legend(const vtr::ColorMap& cmap, ezgl::renderer* g); @@ -859,7 +858,6 @@ void free_draw_structs() { } if (draw_state != nullptr) { - free(draw_state->draw_rr_node); draw_state->draw_rr_node.clear(); } #else @@ -1049,10 +1047,10 @@ static void draw_congestion(ezgl::renderer* g) { //Record min/max congestion float min_congestion_ratio = 1.; float max_congestion_ratio = min_congestion_ratio; - std::vector congested_rr_nodes = collect_congested_rr_nodes(); - for (int inode : congested_rr_nodes) { + std::vector congested_rr_nodes = collect_congested_rr_nodes(); + for (const RRNodeId& inode : congested_rr_nodes) { short occ = route_ctx.rr_node_route_inf[inode].occ(); - short capacity = device_ctx.rr_nodes[inode].capacity(); + short capacity = device_ctx.rr_graph.node_capacity(inode); float congestion_ratio = float(occ) / capacity; @@ -1072,12 +1070,12 @@ static void draw_congestion(ezgl::renderer* g) { //Sort the nodes in ascending order of value for drawing, this ensures high //valued nodes are not overdrawn by lower value ones (e.g-> when zoomed-out far) - auto cmp_ascending_acc_cost = [&](int lhs_node, int rhs_node) { + auto cmp_ascending_acc_cost = [&](const RRNodeId& lhs_node, const RRNodeId& rhs_node) { short lhs_occ = route_ctx.rr_node_route_inf[lhs_node].occ(); - short lhs_capacity = device_ctx.rr_nodes[lhs_node].capacity(); + short lhs_capacity = device_ctx.rr_graph.node_capacity(lhs_node); short rhs_occ = route_ctx.rr_node_route_inf[rhs_node].occ(); - short rhs_capacity = device_ctx.rr_nodes[rhs_node].capacity(); + short rhs_capacity = device_ctx.rr_graph.node_capacity(rhs_node); float lhs_cong_ratio = float(lhs_occ) / lhs_capacity; float rhs_cong_ratio = float(rhs_occ) / rhs_capacity; @@ -1089,7 +1087,7 @@ static void draw_congestion(ezgl::renderer* g) { if (draw_state->show_congestion == DRAW_CONGESTED_WITH_NETS) { auto rr_node_nets = collect_rr_node_nets(); - for (int inode : congested_rr_nodes) { + for (const RRNodeId& inode : congested_rr_nodes) { for (ClusterNetId net : rr_node_nets[inode]) { ezgl::color color = kelly_max_contrast_colors[size_t(net) % kelly_max_contrast_colors.size()]; draw_state->net_color[net] = color; @@ -1099,7 +1097,7 @@ static void draw_congestion(ezgl::renderer* g) { drawroute(HIGHLIGHTED, g); //Reset colors - for (int inode : congested_rr_nodes) { + for (const RRNodeId& inode : congested_rr_nodes) { for (ClusterNetId net : rr_node_nets[inode]) { draw_state->net_color[net] = DEFAULT_RR_NODE_COLOR; } @@ -1109,9 +1107,9 @@ static void draw_congestion(ezgl::renderer* g) { } //Draw each congested node - for (int inode : congested_rr_nodes) { + for (const RRNodeId& inode : congested_rr_nodes) { short occ = route_ctx.rr_node_route_inf[inode].occ(); - short capacity = device_ctx.rr_nodes[inode].capacity(); + short capacity = device_ctx.rr_graph.node_capacity(inode); float congestion_ratio = float(occ) / capacity; @@ -1120,7 +1118,7 @@ static void draw_congestion(ezgl::renderer* g) { ezgl::color color = to_ezgl_color(cmap->color(congestion_ratio)); - switch (device_ctx.rr_nodes[inode].type()) { + switch (device_ctx.rr_graph.node_type(inode)) { case CHANX: //fallthrough case CHANY: draw_rr_chan(inode, color, g); @@ -1159,18 +1157,18 @@ static void draw_routing_costs(ezgl::renderer* g) { float min_cost = std::numeric_limits::infinity(); float max_cost = -min_cost; - std::vector rr_node_costs(device_ctx.rr_graph.nodes().size(), 0.); - for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) { + vtr::vector rr_node_costs(device_ctx.rr_graph.nodes().size(), 0.); + for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { float cost = 0.; if (draw_state->show_routing_costs == DRAW_TOTAL_ROUTING_COSTS || draw_state->show_routing_costs == DRAW_LOG_TOTAL_ROUTING_COSTS) { - int cost_index = device_ctx.rr_nodes[inode].cost_index(); + int cost_index = device_ctx.rr_graph.node_cost_index(inode); cost = device_ctx.rr_indexed_data[cost_index].base_cost + route_ctx.rr_node_route_inf[inode].acc_cost + route_ctx.rr_node_route_inf[inode].pres_cost; } else if (draw_state->show_routing_costs == DRAW_BASE_ROUTING_COSTS) { - int cost_index = device_ctx.rr_nodes[inode].cost_index(); + int cost_index = device_ctx.rr_graph.node_cost_index(inode); cost = device_ctx.rr_indexed_data[cost_index].base_cost; } else if (draw_state->show_routing_costs == DRAW_ACC_ROUTING_COSTS @@ -1194,7 +1192,7 @@ static void draw_routing_costs(ezgl::renderer* g) { } //Hide min value, draw_rr_costs() ignores NaN's - for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) { + for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { if (rr_node_costs[inode] == min_cost) { rr_node_costs[inode] = NAN; } @@ -1292,10 +1290,10 @@ void draw_rr(ezgl::renderer* g) { g->set_line_dash(ezgl::line_dash::none); - for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) { + for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { if (!draw_state->draw_rr_node[inode].node_highlighted) { /* If not highlighted node, assign color based on type. */ - switch (device_ctx.rr_nodes[inode].type()) { + switch (device_ctx.rr_graph.node_type(inode)) { case CHANX: case CHANY: draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR; @@ -1312,7 +1310,7 @@ void draw_rr(ezgl::renderer* g) { } /* Now call drawing routines to draw the node. */ - switch (device_ctx.rr_nodes[inode].type()) { + switch (device_ctx.rr_graph.node_type(inode)) { case SOURCE: case SINK: break; /* Don't draw. */ @@ -1338,7 +1336,7 @@ void draw_rr(ezgl::renderer* g) { default: vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__, - "in draw_rr: Unexpected rr_node type: %d.\n", device_ctx.rr_nodes[inode].type()); + "in draw_rr: Unexpected rr_node type: %d.\n", device_ctx.rr_graph.node_type(inode)); } } @@ -1434,7 +1432,7 @@ static void draw_rr_chan(const RRNodeId& inode, const ezgl::color color, ezgl::r if (switchpoint_min == 0) { if (dir != BI_DIRECTION) { //Draw a mux at the start of each wire, labelled with it's size (#inputs) - draw_mux_with_size(start, mux_dir, WIRE_DRAWING_WIDTH, device_ctx.rr_nodes[inode].fan_in(), g); + draw_mux_with_size(start, mux_dir, WIRE_DRAWING_WIDTH, device_ctx.rr_graph.node_in_edges(inode).size(), g); } } else { //Draw arrows and label with switch point @@ -1590,7 +1588,7 @@ static void draw_rr_edges(const RRNodeId& inode, ezgl::renderer* g) { } else { g->set_color(blk_DARKGREEN); } - switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge); + switch_type = size_t(device_ctx.rr_graph.edge_switch(iedge)); draw_chanx_to_chanx_edge(inode, to_node, to_ptc_num, switch_type, g); break; @@ -1607,7 +1605,7 @@ static void draw_rr_edges(const RRNodeId& inode, ezgl::renderer* g) { } else { g->set_color(blk_DARKGREEN); } - switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge); + switch_type = size_t(device_ctx.rr_graph.edge_switch(iedge)); draw_chanx_to_chany_edge(inode, from_ptc_num, to_node, to_ptc_num, FROM_X_TO_Y, switch_type, g); break; @@ -1660,7 +1658,7 @@ static void draw_rr_edges(const RRNodeId& inode, ezgl::renderer* g) { } else { g->set_color(blk_DARKGREEN); } - switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge); + switch_type = size_t(device_ctx.rr_graph.edge_switch(iedge)); draw_chanx_to_chany_edge(to_node, to_ptc_num, inode, from_ptc_num, FROM_Y_TO_X, switch_type, g); break; @@ -1678,7 +1676,7 @@ static void draw_rr_edges(const RRNodeId& inode, ezgl::renderer* g) { } else { g->set_color(blk_DARKGREEN); } - switch_type = device_ctx.rr_nodes[inode].edge_switch(iedge); + switch_type = size_t(device_ctx.rr_graph.edge_switch(iedge)); draw_chany_to_chany_edge(inode, to_node, to_ptc_num, switch_type, g); break; @@ -1955,7 +1953,7 @@ ezgl::rectangle draw_get_rr_chan_bbox(const RRNodeId& inode) { t_draw_coords* draw_coords = get_draw_coords_vars(); auto& device_ctx = g_vpr_ctx.device(); - switch (device_ctx.rr_nodes[inode].type()) { + switch (device_ctx.rr_graph.node_type(inode)) { case CHANX: left = draw_coords->tile_x[device_ctx.rr_graph.node_xlow(inode)]; right = draw_coords->tile_x[device_ctx.rr_graph.node_xhigh(inode)] @@ -2012,7 +2010,7 @@ static void draw_rr_switch(float from_x, float from_y, float to_x, float to_y, b } } -static void draw_rr_pin(RRNodeId& inode, const ezgl::color& color, ezgl::renderer* g) { +static void draw_rr_pin(const RRNodeId& inode, const ezgl::color& color, ezgl::renderer* g) { /* Draws an IPIN or OPIN rr_node. Note that the pin can appear on more * * than one side of a clb. Also note that this routine can change the * * current color to BLACK. */ @@ -2066,7 +2064,7 @@ void draw_get_rr_pin_coords(const RRNodeId& inode, float* xcen, float* ycen) { step = (float)(draw_coords->get_tile_width()) / (float)(type->num_pins + type->capacity); offset = (ipin + k + 1) * step; - switch (node->side()) { + switch (device_ctx.rr_graph.node_side(inode)) { case LEFT: yc += offset; break; @@ -2087,7 +2085,8 @@ void draw_get_rr_pin_coords(const RRNodeId& inode, float* xcen, float* ycen) { default: vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__, - "in draw_get_rr_pin_coords: Unexpected side %s.\n", node->side_string()); + "in draw_get_rr_pin_coords: Unexpected side %s.\n", + SIDE_STRING[device_ctx.rr_graph.node_side(inode)]); break; } @@ -2221,7 +2220,7 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren std::vector edges = device_ctx.rr_graph.find_edges(prev_node, inode); VTR_ASSERT(1 == edges.size()); - auto switch_type = device_ctx.rr_graph.edge_switch(edges[0]); + auto switch_type = size_t(device_ctx.rr_graph.edge_switch(edges[0])); switch (rr_type) { case OPIN: { @@ -2230,7 +2229,7 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren } case IPIN: { draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g); - if (device_ctx.rr_nodes[prev_node].type() == OPIN) { + if (device_ctx.rr_graph.node_type(prev_node) == OPIN) { draw_pin_to_pin(prev_node, inode, g); } else { draw_pin_to_chan_edge(inode, prev_node, g); @@ -2239,7 +2238,7 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren } case CHANX: { if (draw_state->draw_route_type == GLOBAL) - chanx_track[device_ctx.rr_nodes[inode].xlow()][device_ctx.rr_nodes[inode].ylow()]++; + chanx_track[device_ctx.rr_graph.node_xlow(inode)][device_ctx.rr_graph.node_ylow(inode)]++; int itrack = get_track_num(inode, chanx_track, chany_track); draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g); @@ -2390,14 +2389,14 @@ void highlight_nets(char* message, const RRNodeId& hit_node) { * fan_in into the node in blue and fan_out from the node in red. If de-highlighted, * de-highlight its fan_in and fan_out. */ -void draw_highlight_fan_in_fan_out(const std::set& nodes) { +void draw_highlight_fan_in_fan_out(const std::set& nodes) { t_draw_state* draw_state = get_draw_state_vars(); auto& device_ctx = g_vpr_ctx.device(); for (auto node : nodes) { /* Highlight the fanout nodes in red. */ - for (t_edge_size iedge = 0, l = device_ctx.rr_nodes[node].num_edges(); iedge < l; iedge++) { - int fanout_node = device_ctx.rr_nodes[node].edge_sink_node(iedge); + for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(node)) { + RRNodeId fanout_node = device_ctx.rr_graph.edge_sink_node(iedge); if (draw_state->draw_rr_node[node].color == ezgl::MAGENTA && draw_state->draw_rr_node[fanout_node].color != ezgl::MAGENTA) { // If node is highlighted, highlight its fanout @@ -2411,9 +2410,9 @@ void draw_highlight_fan_in_fan_out(const std::set& nodes) { } /* Highlight the nodes that can fanin to this node in blue. */ - for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) { - for (t_edge_size iedge = 0, l = device_ctx.rr_nodes[inode].num_edges(); iedge < l; iedge++) { - int fanout_node = device_ctx.rr_nodes[inode].edge_sink_node(iedge); + for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { + for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(node)) { + RRNodeId fanout_node = device_ctx.rr_graph.edge_sink_node(iedge); if (fanout_node == node) { if (draw_state->draw_rr_node[node].color == ezgl::MAGENTA && draw_state->draw_rr_node[inode].color != ezgl::MAGENTA) { // If node is highlighted, highlight its fanin @@ -2436,8 +2435,8 @@ void draw_highlight_fan_in_fan_out(const std::set& nodes) { * * It returns the hit RR node's ID (or OPEN if no hit) */ -static int draw_check_rr_node_hit(float click_x, float click_y) { - int hit_node = OPEN; +static RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { + RRNodeId hit_node = RRNodeId::INVALID(); ezgl::rectangle bound_box; t_draw_coords* draw_coords = get_draw_coords_vars(); @@ -2489,20 +2488,20 @@ static int draw_check_rr_node_hit(float click_x, float click_y) { return hit_node; } -std::set draw_expand_non_configurable_rr_nodes(int from_node) { - std::set expanded_nodes; +std::set draw_expand_non_configurable_rr_nodes(const RRNodeId& from_node) { + std::set expanded_nodes; draw_expand_non_configurable_rr_nodes_recurr(from_node, expanded_nodes); return expanded_nodes; } -void draw_expand_non_configurable_rr_nodes_recurr(int from_node, std::set& expanded_nodes) { +void draw_expand_non_configurable_rr_nodes_recurr(const RRNodeId& from_node, std::set& expanded_nodes) { auto& device_ctx = g_vpr_ctx.device(); expanded_nodes.insert(from_node); - for (t_edge_size iedge = 0; iedge < device_ctx.rr_nodes[from_node].num_edges(); ++iedge) { - bool edge_configurable = device_ctx.rr_nodes[from_node].edge_is_configurable(iedge); - int to_node = device_ctx.rr_nodes[from_node].edge_sink_node(iedge); + for (const RREdgeId& iedge : device_ctx.rr_graph.node_out_edges(from_node)) { + bool edge_configurable = device_ctx.rr_graph.edge_is_configurable(iedge); + RRNodeId to_node = device_ctx.rr_graph.edge_sink_node(iedge); if (!edge_configurable && !expanded_nodes.count(to_node)) { draw_expand_non_configurable_rr_nodes_recurr(to_node, expanded_nodes); @@ -2525,7 +2524,7 @@ static bool highlight_rr_nodes(float x, float y) { } // Check which rr_node (if any) was clicked on. - int hit_node = draw_check_rr_node_hit(x, y); + RRNodeId hit_node = draw_check_rr_node_hit(x, y); return highlight_rr_nodes(hit_node); } @@ -2629,9 +2628,9 @@ void act_on_mouse_move(ezgl::application* app, GdkEventButton* event, double x, t_draw_state* draw_state = get_draw_state_vars(); if (draw_state->draw_rr_toggle != DRAW_NO_RR) { - int hit_node = draw_check_rr_node_hit(x, y); + RRNodeId hit_node = draw_check_rr_node_hit(x, y); - if (hit_node != OPEN) { + if (hit_node != RRNodeId::INVALID()) { //Update message std::string info = describe_rr_node(hit_node); @@ -2723,9 +2722,9 @@ void deselect_all() { for (auto net_id : cluster_ctx.clb_nlist.nets()) draw_state->net_color[net_id] = ezgl::BLACK; - for (size_t i = 0; i < device_ctx.rr_graph.nodes().size(); i++) { - draw_state->draw_rr_node[i].color = DEFAULT_RR_NODE_COLOR; - draw_state->draw_rr_node[i].node_highlighted = false; + for (const RRNodeId& node : device_ctx.rr_graph.nodes()) { + draw_state->draw_rr_node[node].color = DEFAULT_RR_NODE_COLOR; + draw_state->draw_rr_node[node].node_highlighted = false; } get_selected_sub_block_info().clear(); } @@ -2827,7 +2826,7 @@ static void draw_pin_to_chan_edge(const RRNodeId& pin_node, const RRNodeId& chan ezgl::rectangle chan_bbox = draw_get_rr_chan_bbox(chan_node); float x2 = 0, y2 = 0; - switch (chan_rr.type()) { + switch (rr_graph.node_type(chan_node)) { case CHANX: { y1 += draw_pin_offset; y2 = chan_bbox.bottom(); @@ -3138,15 +3137,15 @@ static void draw_routed_timing_edge_connection(tatum::NodeId src_tnode, tatum::N //Now that we have the CLB source and sink pins, we need to grab all the points on the routing connecting the pins VTR_ASSERT(cluster_ctx.clb_nlist.net_driver_block(net_id) == clb_src_block); - std::vector routed_rr_nodes = trace_routed_connection_rr_nodes(net_id, 0, sink_net_pin_index); + std::vector routed_rr_nodes = trace_routed_connection_rr_nodes(net_id, 0, sink_net_pin_index); //Mark all the nodes highlighted t_draw_state* draw_state = get_draw_state_vars(); - for (int inode : routed_rr_nodes) { + for (const RRNodeId& inode : routed_rr_nodes) { draw_state->draw_rr_node[inode].color = color; } - draw_partial_route((std::vector)routed_rr_nodes, (ezgl::renderer*)g); + draw_partial_route((std::vector)routed_rr_nodes, (ezgl::renderer*)g); } else { //Connection entirely within the CLB, we don't draw the internal routing so treat it as a fly-line VTR_ASSERT(clb_src_block == clb_sink_block); @@ -3157,7 +3156,7 @@ static void draw_routed_timing_edge_connection(tatum::NodeId src_tnode, tatum::N } //Returns the set of rr nodes which connect driver to sink -static std::vector trace_routed_connection_rr_nodes(const ClusterNetId net_id, const int driver_pin, const int sink_pin) { +static std::vector trace_routed_connection_rr_nodes(const ClusterNetId net_id, const int driver_pin, const int sink_pin) { auto& route_ctx = g_vpr_ctx.routing(); bool allocated_route_tree_structs = alloc_route_tree_timing_structs(true); //Needed for traceback_to_route_tree @@ -3165,11 +3164,11 @@ static std::vector trace_routed_connection_rr_nodes(const ClusterNetId net_ //Conver the traceback into an easily search-able t_rt_node* rt_root = traceback_to_route_tree(net_id); - VTR_ASSERT(rt_root && rt_root->inode == route_ctx.net_rr_terminals[net_id][driver_pin]); + VTR_ASSERT(rt_root && rt_root->inode == RRNodeId(route_ctx.net_rr_terminals[net_id][driver_pin])); - int sink_rr_node = route_ctx.net_rr_terminals[net_id][sink_pin]; + RRNodeId sink_rr_node = RRNodeId(route_ctx.net_rr_terminals[net_id][sink_pin]); - std::vector rr_nodes_on_path; + std::vector rr_nodes_on_path; //Collect the rr nodes trace_routed_connection_rr_nodes_recurr(rt_root, sink_rr_node, rr_nodes_on_path); @@ -3188,7 +3187,7 @@ static std::vector trace_routed_connection_rr_nodes(const ClusterNetId net_ //Helper function for trace_routed_connection_rr_nodes //Adds the rr nodes linking rt_node to sink_rr_node to rr_nodes_on_path //Returns true if rt_node is on the path -bool trace_routed_connection_rr_nodes_recurr(const t_rt_node* rt_node, int sink_rr_node, std::vector& rr_nodes_on_path) { +bool trace_routed_connection_rr_nodes_recurr(const t_rt_node* rt_node, const RRNodeId& sink_rr_node, std::vector& rr_nodes_on_path) { //DFS from the current rt_node to the sink_rr_node, when the sink is found trace back the used rr nodes if (rt_node->inode == sink_rr_node) { @@ -3211,18 +3210,6 @@ bool trace_routed_connection_rr_nodes_recurr(const t_rt_node* rt_node, int sink_ return false; //Not on path to sink } -//Find the edge between two rr nodes -static t_edge_size find_edge(int prev_inode, int inode) { - auto& device_ctx = g_vpr_ctx.device(); - for (t_edge_size iedge = 0; iedge < device_ctx.rr_nodes[prev_inode].num_edges(); ++iedge) { - if (device_ctx.rr_nodes[prev_inode].edge_sink_node(iedge) == inode) { - return iedge; - } - } - VTR_ASSERT(false); - return OPEN; -} - ezgl::color to_ezgl_color(vtr::Color color) { return ezgl::color(color.r * 255, color.g * 255, color.b * 255); } @@ -3548,7 +3535,13 @@ static void draw_rr_costs(ezgl::renderer* g, const vtr::vector& //Draw the nodes in ascending order of value, this ensures high valued nodes //are not overdrawn by lower value ones (e.g-> when zoomed-out far) - std::vector nodes = device_ctx.rr_graph.nodes(); + std::vector nodes; + /* Xifan Tang - TODO: This is not efficient, + * we should be able to give a constant vector from rr_graph object directly + */ + for (const RRNodeId& node : device_ctx.rr_graph.nodes()) { + nodes.push_back(node); + } auto cmp_ascending_cost = [&](const RRNodeId& lhs_node, const RRNodeId& rhs_node) { if (lowest_cost_first) { return rr_costs[lhs_node] > rr_costs[rhs_node]; diff --git a/vpr/src/draw/draw.h b/vpr/src/draw/draw.h index 98c908ba4..39458b968 100644 --- a/vpr/src/draw/draw.h +++ b/vpr/src/draw/draw.h @@ -60,8 +60,8 @@ void draw_screen(); ezgl::rectangle draw_get_rr_chan_bbox(const RRNodeId& inode); void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId blk_id); void highlight_nets(char* message, const RRNodeId& hit_node); -void draw_highlight_fan_in_fan_out(const std::set& nodes); -std::set draw_expand_non_configurable_rr_nodes(int hit_node); +void draw_highlight_fan_in_fan_out(const std::set& nodes); +std::set draw_expand_non_configurable_rr_nodes(const RRNodeId& hit_node); void deselect_all(); // toggle functions diff --git a/vpr/src/draw/search_bar.cpp b/vpr/src/draw/search_bar.cpp index aaa591c20..a7ff3831b 100644 --- a/vpr/src/draw/search_bar.cpp +++ b/vpr/src/draw/search_bar.cpp @@ -74,8 +74,8 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) { return; } - highlight_rr_nodes(rr_node_id); - auto_zoom_rr_node(rr_node_id); + highlight_rr_nodes(RRNodeId(rr_node_id)); + auto_zoom_rr_node(RRNodeId(rr_node_id)); } else if (search_type == "Block ID") { @@ -125,12 +125,12 @@ void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app) { app->refresh_drawing(); } -bool highlight_rr_nodes(int hit_node) { +bool highlight_rr_nodes(const RRNodeId& hit_node) { t_draw_state* draw_state = get_draw_state_vars(); char message[250] = ""; - if (hit_node != OPEN) { + if (hit_node != RRNodeId::INVALID()) { auto nodes = draw_expand_non_configurable_rr_nodes(hit_node); for (auto node : nodes) { if (draw_state->draw_rr_node[node].color != ezgl::MAGENTA) { @@ -177,21 +177,21 @@ bool highlight_rr_nodes(int hit_node) { return true; } -void auto_zoom_rr_node(int rr_node_id) { +void auto_zoom_rr_node(const RRNodeId& rr_node_id) { t_draw_coords* draw_coords = get_draw_coords_vars(); auto& device_ctx = g_vpr_ctx.device(); ezgl::rectangle rr_node; // find the location of the node - switch (device_ctx.rr_nodes[rr_node_id].type()) { + switch (device_ctx.rr_graph.node_type(rr_node_id)) { case IPIN: case OPIN: { - int i = device_ctx.rr_nodes[rr_node_id].xlow(); - int j = device_ctx.rr_nodes[rr_node_id].ylow(); + int i = device_ctx.rr_graph.node_xlow(rr_node_id); + int j = device_ctx.rr_graph.node_ylow(rr_node_id); t_physical_tile_type_ptr type = device_ctx.grid[i][j].type; int width_offset = device_ctx.grid[i][j].width_offset; int height_offset = device_ctx.grid[i][j].height_offset; - int ipin = device_ctx.rr_nodes[rr_node_id].ptc_num(); + int ipin = device_ctx.rr_graph.node_ptc_num(rr_node_id); float xcen, ycen; int iside; diff --git a/vpr/src/draw/search_bar.h b/vpr/src/draw/search_bar.h index c908e78c9..ac3f771cf 100644 --- a/vpr/src/draw/search_bar.h +++ b/vpr/src/draw/search_bar.h @@ -11,8 +11,8 @@ # include "draw_color.h" void search_and_highlight(GtkWidget* /*widget*/, ezgl::application* app); -bool highlight_rr_nodes(int hit_node); -void auto_zoom_rr_node(int rr_node_id); +bool highlight_rr_nodes(const RRNodeId& hit_node); +void auto_zoom_rr_node(const RRNodeId& rr_node_id); void highlight_blocks(ClusterBlockId clb_index); void highlight_nets(ClusterNetId net_id); void highlight_nets(std::string net_name); diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp index d3cdad215..dd55adca4 100644 --- a/vpr/src/place/timing_place_lookup.cpp +++ b/vpr/src/place/timing_place_lookup.cpp @@ -34,6 +34,8 @@ #include "router_delay_profiling.h" #include "place_delay_model.h" +#include "rr_graph_obj_util.h" + /*To compute delay between blocks we calculate the delay between */ /*different nodes in the FPGA. From this procedure we generate * a lookup table which tells us the delay between different locations in*/ @@ -113,8 +115,8 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct, t_physical_tile_type_ptr to_type, int to_pin, int to_pin_class, - int* src_rr, - int* sink_rr); + RRNodeId& src_rr, + RRNodeId& sink_rr); static bool verify_delta_delays(const vtr::Matrix& delta_delays); @@ -741,8 +743,8 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct, t_physical_tile_type_ptr to_type, int to_pin, int to_pin_class, - int* src_rr, - int* sink_rr) { + RRNodeId& src_rr, + RRNodeId& sink_rr) { VTR_ASSERT(from_type != nullptr); VTR_ASSERT(to_type != nullptr); @@ -765,10 +767,10 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct, //(with multi-width/height blocks pins may not exist at all locations) bool from_pin_found = false; if (direct->from_side != NUM_SIDES) { - int from_pin_rr = get_rr_node_index(device_ctx.rr_node_indices, from_x, from_y, OPIN, from_pin, direct->from_side); - from_pin_found = (from_pin_rr != OPEN); + RRNodeId from_pin_rr = device_ctx.rr_graph.find_node(from_x, from_y, OPIN, from_pin, direct->from_side); + from_pin_found = (from_pin_rr != RRNodeId::INVALID()); } else { - std::vector from_pin_rrs = get_rr_node_indices(device_ctx.rr_node_indices, from_x, from_y, OPIN, from_pin); + std::vector from_pin_rrs = find_rr_graph_nodes(device_ctx.rr_graph, from_x, from_y, OPIN, from_pin); from_pin_found = !from_pin_rrs.empty(); } if (!from_pin_found) continue; @@ -782,10 +784,10 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct, //(with multi-width/height blocks pins may not exist at all locations) bool to_pin_found = false; if (direct->to_side != NUM_SIDES) { - int to_pin_rr = get_rr_node_index(device_ctx.rr_node_indices, to_x, to_y, IPIN, to_pin, direct->to_side); - to_pin_found = (to_pin_rr != OPEN); + RRNodeId to_pin_rr = device_ctx.rr_graph.find_node(to_x, to_y, IPIN, to_pin, direct->to_side); + to_pin_found = (to_pin_rr != RRNodeId::INVALID()); } else { - std::vector to_pin_rrs = get_rr_node_indices(device_ctx.rr_node_indices, to_x, to_y, IPIN, to_pin); + std::vector to_pin_rrs = find_rr_graph_nodes(device_ctx.rr_graph, to_x, to_y, IPIN, to_pin); to_pin_found = !to_pin_rrs.empty(); } if (!to_pin_found) continue; @@ -822,14 +824,14 @@ static bool find_direct_connect_sample_locations(const t_direct_inf* direct, //Find a source/sink RR node associated with the pins of the direct // - auto source_rr_nodes = get_rr_node_indices(device_ctx.rr_node_indices, from_x, from_y, SOURCE, from_pin_class); + std::vector source_rr_nodes = find_rr_graph_nodes(device_ctx.rr_graph, from_x, from_y, SOURCE, from_pin_class); VTR_ASSERT(source_rr_nodes.size() > 0); - auto sink_rr_nodes = get_rr_node_indices(device_ctx.rr_node_indices, to_x, to_y, SINK, to_pin_class); + std::vector sink_rr_nodes = find_rr_graph_nodes(device_ctx.rr_graph, to_x, to_y, SINK, to_pin_class); VTR_ASSERT(sink_rr_nodes.size() > 0); - *src_rr = source_rr_nodes[0]; - *sink_rr = sink_rr_nodes[0]; + src_rr = source_rr_nodes[0]; + sink_rr = sink_rr_nodes[0]; return true; } @@ -884,7 +886,7 @@ void OverrideDelayModel::compute_override_delay_model( //sampled_rr_pairs and skipping them if they occur multiple times. int missing_instances = 0; int missing_paths = 0; - std::set> sampled_rr_pairs; + std::set> sampled_rr_pairs; for (int iconn = 0; iconn < num_conns; ++iconn) { //Find the associated pins int from_pin = find_pin(from_type, from_port.port_name(), from_port.port_low_index() + iconn); @@ -899,9 +901,9 @@ void OverrideDelayModel::compute_override_delay_model( int to_pin_class = find_pin_class(to_type, to_port.port_name(), to_port.port_low_index() + iconn, RECEIVER); VTR_ASSERT(to_pin_class != OPEN); - int src_rr = OPEN; - int sink_rr = OPEN; - bool found_sample_points = find_direct_connect_sample_locations(direct, from_type, from_pin, from_pin_class, to_type, to_pin, to_pin_class, &src_rr, &sink_rr); + RRNodeId src_rr = RRNodeId::INVALID(); + RRNodeId sink_rr = RRNodeId::INVALID(); + bool found_sample_points = find_direct_connect_sample_locations(direct, from_type, from_pin, from_pin_class, to_type, to_pin, to_pin_class, src_rr, sink_rr); if (!found_sample_points) { ++missing_instances; @@ -912,8 +914,8 @@ void OverrideDelayModel::compute_override_delay_model( //sampled the associated source/sink pair and don't need to do so again if (sampled_rr_pairs.count({src_rr, sink_rr})) continue; - VTR_ASSERT(src_rr != OPEN); - VTR_ASSERT(sink_rr != OPEN); + VTR_ASSERT(src_rr != RRNodeId::INVALID()); + VTR_ASSERT(sink_rr != RRNodeId::INVALID()); float direct_connect_delay = std::numeric_limits::quiet_NaN(); bool found_routing_path = route_profiler.calculate_delay(src_rr, sink_rr, router_opts2, &direct_connect_delay); diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 40eada542..39373cb76 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -346,14 +346,14 @@ bool feasible_routing() { } //Returns all RR nodes in the current routing which are congested -std::vector collect_congested_rr_nodes() { +std::vector collect_congested_rr_nodes() { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.routing(); - std::vector congested_rr_nodes; - for (size_t inode = 0; inode < device_ctx.rr_graph.nodes().size(); inode++) { + std::vector congested_rr_nodes; + for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { short occ = route_ctx.rr_node_route_inf[inode].occ(); - short capacity = device_ctx.rr_nodes[inode].capacity(); + short capacity = device_ctx.rr_graph.node_capacity(inode); if (occ > capacity) { congested_rr_nodes.push_back(inode); @@ -364,16 +364,16 @@ std::vector collect_congested_rr_nodes() { /* Returns a vector from [0..device_ctx.rr_graph.nodes().size()-1] containing the set * of nets using each RR node */ -std::vector> collect_rr_node_nets() { +vtr::vector> collect_rr_node_nets() { auto& device_ctx = g_vpr_ctx.device(); auto& route_ctx = g_vpr_ctx.routing(); auto& cluster_ctx = g_vpr_ctx.clustering(); - std::vector> rr_node_nets(device_ctx.rr_graph.nodes().size()); + vtr::vector> rr_node_nets(device_ctx.rr_graph.nodes().size()); for (ClusterNetId inet : cluster_ctx.clb_nlist.nets()) { t_trace* trace_elem = route_ctx.trace[inet].head; while (trace_elem) { - int rr_node = trace_elem->index; + const RRNodeId& rr_node = trace_elem->index; rr_node_nets[rr_node].insert(inet); diff --git a/vpr/src/route/route_export.h b/vpr/src/route/route_export.h index ec68f83b8..187ca5087 100644 --- a/vpr/src/route/route_export.h +++ b/vpr/src/route/route_export.h @@ -29,9 +29,9 @@ bool try_route(int width_fac, bool feasible_routing(); -std::vector collect_congested_rr_nodes(); +std::vector collect_congested_rr_nodes(); -std::vector> collect_rr_node_nets(); +vtr::vector> collect_rr_node_nets(); t_clb_opins_used alloc_route_structs(); diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index 6bb9892ed..e70e70d01 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -2526,53 +2526,53 @@ static vtr::NdMatrix, 4> alloc_and_load_track_to_pin_lookup(vtr return track_to_pin_lookup; } -std::string describe_rr_node(int inode) { +std::string describe_rr_node(const RRNodeId& inode) { auto& device_ctx = g_vpr_ctx.device(); - std::string msg = vtr::string_fmt("RR node: %d", inode); + std::string msg = vtr::string_fmt("RR node: %ld", size_t(inode)); - const auto& rr_node = device_ctx.rr_nodes[inode]; + const RRGraph& rr_graph = device_ctx.rr_graph; - msg += vtr::string_fmt(" type: %s", rr_node.type_string()); + msg += vtr::string_fmt(" type: %s", rr_node_typename[rr_graph.node_type(inode)]); - msg += vtr::string_fmt(" location: (%d,%d)", rr_node.xlow(), rr_node.ylow()); - if (rr_node.xlow() != rr_node.xhigh() || rr_node.ylow() != rr_node.yhigh()) { - msg += vtr::string_fmt(" <-> (%d,%d)", rr_node.xhigh(), rr_node.yhigh()); + msg += vtr::string_fmt(" location: (%d,%d)", rr_graph.node_xlow(inode), rr_graph.node_ylow(inode)); + if (rr_graph.node_xlow(inode) != rr_graph.node_xhigh(inode) || rr_graph.node_ylow(inode) != rr_graph.node_yhigh(inode)) { + msg += vtr::string_fmt(" <-> (%d,%d)", rr_graph.node_xhigh(inode), rr_graph.node_yhigh(inode)); } - if (rr_node.type() == CHANX || rr_node.type() == CHANY) { - int cost_index = rr_node.cost_index(); + if (rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) { + int cost_index = rr_graph.node_cost_index(inode); int seg_index = device_ctx.rr_indexed_data[cost_index].seg_index; if (seg_index < (int)device_ctx.arch->Segments.size()) { msg += vtr::string_fmt(" track: %d len: %d longline: %d seg_type: %s dir: %s", - rr_node.track_num(), - rr_node.length(), + rr_graph.node_track_num(inode), + rr_graph.node_length(inode), device_ctx.arch->Segments[seg_index].longline, device_ctx.arch->Segments[seg_index].name.c_str(), - rr_node.direction_string()); + DIRECTION_STRING_WRITE_XML[rr_graph.node_direction(inode)]); } else { msg += vtr::string_fmt(" track: %d len: %d seg_type: ILLEGAL_SEG_INDEX %d dir: %s", - rr_node.track_num(), - rr_node.length(), + rr_graph.node_track_num(inode), + rr_graph.node_length(inode), seg_index, - rr_node.direction_string()); + DIRECTION_STRING_WRITE_XML[rr_graph.node_direction(inode)]); } - } else if (rr_node.type() == IPIN || rr_node.type() == OPIN) { - auto type = device_ctx.grid[rr_node.xlow()][rr_node.ylow()].type; - std::string pin_name = block_type_pin_index_to_name(type, rr_node.pin_num()); + } else if (rr_graph.node_type(inode) == IPIN || rr_graph.node_type(inode) == OPIN) { + auto type = device_ctx.grid[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)].type; + std::string pin_name = block_type_pin_index_to_name(type, rr_graph.node_pin_num(inode)); msg += vtr::string_fmt(" pin: %d pin_name: %s", - rr_node.pin_num(), + rr_graph.node_pin_num(inode), pin_name.c_str()); } else { - VTR_ASSERT(rr_node.type() == SOURCE || rr_node.type() == SINK); + VTR_ASSERT(rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK); - msg += vtr::string_fmt(" class: %d", rr_node.class_num()); + msg += vtr::string_fmt(" class: %d", rr_graph.node_class_num(inode)); } - msg += vtr::string_fmt(" capacity: %d", rr_node.capacity()); + msg += vtr::string_fmt(" capacity: %d", rr_graph.node_capacity(inode)); return msg; } diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index f55a64f7f..1f60b1afc 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -43,7 +43,7 @@ void create_rr_graph(const t_graph_type graph_type, void free_rr_graph(); //Returns a brief one-line summary of an RR node -std::string describe_rr_node(int inode); +std::string describe_rr_node(const RRNodeId& inode); void init_fan_in(std::vector& L_rr_node, const int num_rr_nodes);