[Benchmark] Bug fix in pipelined and2 benchmark

openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.act

@@ -1,7 +1,9 @@
-a 0.5 0.2
-b 0.5 0.2
-c 0.25 0.1
-a_reg 0.5 0.2
-b_reg 0.5 0.2
-c_reg 0.25 0.1
 clk 0.500000 2.000000
+a 0.502000 0.197200
+b 0.485400 0.202800
+c 0.248000 0.176800
+a_reg 0.502000 0.197200
+b_reg 0.485400 0.202800
+n10 0.248000 0.043259
+n13 0.502000 0.098994
+n17 0.485400 0.098439

openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.blif

@@ -1,12 +1,16 @@
+# Benchmark "and2_pipelined" written by ABC on Sun Jan 10 10:26:01 2021
 .model and2_pipelined
 .inputs clk a b
 .outputs c
 
-.latch a a_reg re clk 0
-.latch b b_reg re clk 0
-.latch c_reg c re clk 0
+.latch        n10          c  2
+.latch        n13      a_reg  2
+.latch        n17      b_reg  2
 
-.names a_reg b_reg c_reg
+.names a_reg b_reg n10
 11 1
-
+.names a n13
+1 1
+.names b n17
+1 1
 .end

openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v

@@ -22,7 +22,7 @@ reg c_reg;
 
 always @(posedge clk) begin
   a_reg <= a;
-  b_reg <= a;
+  b_reg <= b;
 end
 
 always @(posedge clk) begin