From 61026dc623d59a8ea873597a96ebfd7d61237f8c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Jul 2019 16:58:11 -0400 Subject: [PATCH 01/21] Update building.md --- tutorials/building.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tutorials/building.md b/tutorials/building.md index bc7bc28a9..7525493a4 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -1,8 +1,8 @@ # How to build? -## Dependancies +## Dependencies -OpenFPGA requires all the dependancies listed below: +OpenFPGA requires all the following dependencies: - autoconf - automake - bash @@ -40,18 +40,18 @@ OpenFPGA requires all the dependancies listed below: ## Docker -If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. A container ready to use can be created with the following command: +If all these dependancies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). To ease customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command: - docker run lnis/open_fpga:release
*Warning: This command is for quick testing. If you want to conserve your work you should certainly use other options as "-v".* -Or a container where you can build OpenFPGA yourself can be created with the following commands: +Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands: - docker build . -t open_fpga - docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash
[*docker download link*](https://www.docker.com/products/docker-desktop) ## Building -To build the tool you have to be in OpenFPGA folder and do: +To build the tool you have to go in OpenFPGA folder and do: - mkdir build && cd build - cmake .. -DCMAKE_BUILD_TYPE=debug - make (*WARNING using docker you cannot use "make -j", errors will happen*) From 6e1d49d74e2c03cd049a96dc66149ee912b603ad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jul 2019 07:54:23 -0600 Subject: [PATCH 02/21] start to support direct mapping to MUX2 standard cells --- .../fpga_spice/k6_N10_sram_tsmc40nm_TT.xml | 1 + .../SRC/fpga_spice_include/spice_types.h | 3 +- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 4 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 136 +++++++++++++----- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 15 +- vpr7_x2p/vpr/regression_verilog.sh | 2 +- 6 files changed, 120 insertions(+), 41 deletions(-) diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml index f54bab155..5b0b85ae7 100755 --- a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml +++ b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml @@ -269,6 +269,7 @@ + diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index e99869c93..76b58c744 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -55,7 +55,8 @@ enum e_spice_model_pass_gate_logic_type { enum e_spice_model_gate_type { SPICE_MODEL_GATE_AND, - SPICE_MODEL_GATE_OR + SPICE_MODEL_GATE_OR, + SPICE_MODEL_GATE_MUX2 }; /* Transistor-level basic informations*/ diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index 9e3a511bf..c0a79aa23 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -616,8 +616,10 @@ static void ProcessSpiceModelGate(ezxml_t Node, gate_info->type = SPICE_MODEL_GATE_AND; } else if (0 == strcmp(FindProperty(Node,"topology",TRUE),"OR")) { gate_info->type = SPICE_MODEL_GATE_OR; + } else if (0 == strcmp(FindProperty(Node,"topology",TRUE),"MUX2")) { + gate_info->type = SPICE_MODEL_GATE_MUX2; } else { - vpr_printf(TIO_MESSAGE_ERROR,"[LINE %d] Invalid topology of gates. Should be [AND|OR].\n", + vpr_printf(TIO_MESSAGE_ERROR,"[LINE %d] Invalid topology of gates. Should be [AND|OR|MUX2].\n", Node->line); exit(1); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 79a794729..61012c6fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1104,6 +1104,19 @@ void dump_verilog_mux_basis_module(FILE* fp, spice_mux_model->spice_mux_arch, spice_mux_model->size); + /* Exception: if tgate is a standard cell, we skip the basis circuit generation */ + t_spice_model* tgate_spice_model = spice_mux_model->spice_model->pass_gate_logic->spice_model; + if (SPICE_MODEL_GATE == tgate_spice_model->type) { + assert (SPICE_MODEL_GATE_MUX2 == tgate_spice_model->design_tech_info.gate_info->type); + /* Double check the mux structure, which should be tree-like */ + if ( SPICE_MODEL_STRUCTURE_TREE != spice_mux_model->spice_mux_arch->structure ) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of Circuit model (%s) should be tree-like because it is linked to a 2:1 MUX!\n", + __FILE__, __LINE__, spice_mux_model->spice_model->name); + exit(1); + } + return; + } + /* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */ /* if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) { @@ -1228,41 +1241,96 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, out_idx = j/2; /* Each basis mux2to1: svdd sgnd */ fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ - /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { - fprintf(fp, ",\n"); - } - if (true == is_explicit_mapping) { - fprintf(fp, ".in("); - } - /* For intermediate buffers */ - if (TRUE == inter_buf_loc[level]) { - fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */ + /* For MUX2 standard cell */ + t_spice_model* tgate_spice_model = spice_model.pass_gate_logic->spice_model; + /* For non-standard cells */ + if (SPICE_MODEL_GATE == tgate_spice_model->type) { + assert(SPICE_MODEL_GATE_MUX2 == tgate_spice_model->design_tech_info.gate_info->type); + int num_input_port = 0; + int num_output_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + /* Quick check on the number of ports */ + assert(3 == num_input_port); /* A, B and SEL */ + assert(1 == num_output_port); /* OUT */ + + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + fprintf(fp, ",\n"); + } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", input_port[0]->lib_name); + } + /* For intermediate buffers */ + if (TRUE == inter_buf_loc[level]) { + fprintf(fp, "mux2_l%d_in_buf[%d]", level, j); /* input0 */ + } else { + fprintf(fp, "mux2_l%d_in[%d]", level, j); /* input0 */ + } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", input_port[1]->lib_name); + } + /* For intermediate buffers */ + if (TRUE == inter_buf_loc[level]) { + fprintf(fp, "mux2_l%d_in_buf[%d]", level, nextj); /* input1 */ + } else { + fprintf(fp, "mux2_l%d_in[%d]", level, nextj); /* input1 */ + } + if (true == is_explicit_mapping) { + fprintf(fp, "), .%s(", output_port[0]->lib_name); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .%s(", input_port[2]->lib_name); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "));\n"); + } else { + fprintf(fp, ");\n"); + } } else { - fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */ - } - if (true == is_explicit_mapping) { - fprintf(fp, "), .out("); - } else { - fprintf(fp, ", "); - } - fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ - if (true == is_explicit_mapping) { - fprintf(fp, "), .mem("); - } else { - fprintf(fp, ", "); - } - fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ - if (true == is_explicit_mapping) { - fprintf(fp, "), .mem_inv("); - } else { - fprintf(fp, ", "); - } - fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */ - if (true == is_explicit_mapping) { - fprintf(fp, "));\n"); - } else { - fprintf(fp, ");\n"); + assert (SPICE_MODEL_PASSGATE == tgate_spice_model->type); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + fprintf(fp, ",\n"); + } + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + /* For intermediate buffers */ + if (TRUE == inter_buf_loc[level]) { + fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */ + } else { + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */ + } + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, "));\n"); + } else { + fprintf(fp, ");\n"); + } } /* For intermediate buffers */ if (TRUE == inter_buf_loc[nextlevel]) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 67a31e10f..beaaebac5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2921,10 +2921,17 @@ char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, int mux_size, char* postfix) { char* mux_subckt_name = NULL; - mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 - + strlen(my_itoa(mux_size)) + strlen(postfix) + 1)); - sprintf(mux_subckt_name, "%s_size%d%s", - spice_model->name, mux_size, postfix); + /* If the tgate spice model of this MUX is a MUX2 standard cell, + * the mux_subckt name will be the name of the standard cell + */ + if ( SPICE_MODEL_GATE_MUX2 == spice_model->pass_gate_logic->spice_model->type) { + mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name); + } else { + mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 + + strlen(my_itoa(mux_size)) + strlen(postfix) + 1)); + sprintf(mux_subckt_name, "%s_size%d%s", + spice_model->name, mux_size, postfix); + } return mux_subckt_name; } diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index 644c9c3f3..47608013f 100755 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd - # Run VPR -#echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping" +echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping" ./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping cd $fpga_flow_scripts From dcc96bf7f5bc8af0fd63fafa4814fbfe12435491 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jul 2019 08:25:52 -0600 Subject: [PATCH 03/21] bug fixing --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 10 +++++++++- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c | 7 ++++++- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 3 ++- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index 5212a83ee..7304a25b6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -440,7 +440,15 @@ void config_spice_model_input_output_buffers_pass_gate(int num_spice_models, exit(1); } /* Copy the information from found spice model to current spice model*/ - memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic)); + /* copy gate info if this is a standard cell */ + if (SPICE_MODEL_GATE == pgl_spice_model->type) { + assert ( SPICE_MODEL_GATE_MUX2 == pgl_spice_model->design_tech_info.gate_info->type); + spice_model[i].design_tech_info.gate_info = (t_spice_model_gate*)my_calloc(1, sizeof(t_spice_model_gate)); + memcpy(spice_model[i].design_tech_info.gate_info, pgl_spice_model->design_tech_info.gate_info, sizeof(t_spice_model_gate)); + } else { + assert (SPICE_MODEL_PASSGATE == pgl_spice_model->type); + memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic)); + } /* Recover the spice_model_name */ spice_model[i].pass_gate_logic->spice_model_name = my_strdup(pgl_spice_model->name); spice_model[i].pass_gate_logic->spice_model = pgl_spice_model; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 61012c6fb..83e87ecd5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1250,6 +1250,9 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, int num_output_port = 0; t_spice_model_port** input_port = NULL; t_spice_model_port** output_port = NULL; + + input_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); /* Quick check on the number of ports */ assert(3 == num_input_port); /* A, B and SEL */ assert(1 == num_output_port); /* OUT */ @@ -1268,7 +1271,9 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, fprintf(fp, "mux2_l%d_in[%d]", level, j); /* input0 */ } if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", input_port[1]->lib_name); + fprintf(fp, "), .%s(", input_port[1]->lib_name); + } else { + fprintf(fp, ", "); } /* For intermediate buffers */ if (TRUE == inter_buf_loc[level]) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index beaaebac5..0aba462d8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2924,7 +2924,8 @@ char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, /* If the tgate spice model of this MUX is a MUX2 standard cell, * the mux_subckt name will be the name of the standard cell */ - if ( SPICE_MODEL_GATE_MUX2 == spice_model->pass_gate_logic->spice_model->type) { + if ( SPICE_MODEL_GATE == spice_model->pass_gate_logic->spice_model->type) { + assert ( SPICE_MODEL_GATE_MUX2 == spice_model->design_tech_info.gate_info->type); mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name); } else { mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 From a2505ff16ad4a34f908dd488ba2246a2c1ceba97 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jul 2019 08:36:09 -0600 Subject: [PATCH 04/21] turn on std cell explicit port map --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 83e87ecd5..a0b0f3c25 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1256,12 +1256,18 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, /* Quick check on the number of ports */ assert(3 == num_input_port); /* A, B and SEL */ assert(1 == num_output_port); /* OUT */ + + bool use_explicit_port_map; + if ( (true == is_explicit_mapping) + || (TRUE == tgate_spice_model->dump_explicit_port_map) ) { + use_explicit_port_map = true; + } /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map))) { fprintf(fp, ",\n"); } - if (true == is_explicit_mapping) { + if (true == use_explicit_port_map) { fprintf(fp, ".%s(", input_port[0]->lib_name); } /* For intermediate buffers */ @@ -1270,7 +1276,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } else { fprintf(fp, "mux2_l%d_in[%d]", level, j); /* input0 */ } - if (true == is_explicit_mapping) { + if (true == use_explicit_port_map) { fprintf(fp, "), .%s(", input_port[1]->lib_name); } else { fprintf(fp, ", "); @@ -1281,19 +1287,19 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } else { fprintf(fp, "mux2_l%d_in[%d]", level, nextj); /* input1 */ } - if (true == is_explicit_mapping) { + if (true == use_explicit_port_map) { fprintf(fp, "), .%s(", output_port[0]->lib_name); } else { fprintf(fp, ", "); } fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ - if (true == is_explicit_mapping) { + if (true == use_explicit_port_map) { fprintf(fp, "), .%s(", input_port[2]->lib_name); } else { fprintf(fp, ", "); } fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ - if (true == is_explicit_mapping) { + if (true == use_explicit_port_map) { fprintf(fp, "));\n"); } else { fprintf(fp, ");\n"); From 8b8e18a8de14a54ca62961d02008b894e9bf137d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jul 2019 08:59:57 -0600 Subject: [PATCH 05/21] bug fixing for mux subckt names --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 12 +++++----- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 24 +++++++++++++------ .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 3 +++ 3 files changed, 26 insertions(+), 13 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index a0b0f3c25..c66c00f67 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1128,9 +1128,9 @@ void dump_verilog_mux_basis_module(FILE* fp, /* Prepare the basis subckt name: */ - mux_basis_subckt_name = generate_verilog_mux_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_basis_posfix); + mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_basis_posfix); - special_basis_subckt_name = generate_verilog_mux_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_special_basis_posfix); + special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_special_basis_posfix); /* deteremine the number of inputs of basis subckt */ num_input_basis_subckt = spice_mux_model->spice_mux_arch->num_input_basis; @@ -1647,9 +1647,9 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, char* mux_basis_subckt_name = NULL; char* mux_special_basis_subckt_name = NULL; - mux_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix); + mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix); - mux_special_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix); + mux_special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix); /* Make sure we have a valid file handler*/ if (NULL == fp) { @@ -2156,9 +2156,9 @@ void dump_verilog_rram_mux_submodule(FILE* fp, char* mux_basis_subckt_name = NULL; char* mux_special_basis_subckt_name = NULL; - mux_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix); + mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix); - mux_special_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix); + mux_special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix); /* Make sure we have a valid file handler*/ if (NULL == fp) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 0aba462d8..f280af78d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2915,10 +2915,9 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model, return subckt_name; } - /* Generate the subckt name for a MUX module/submodule */ -char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, - int mux_size, char* postfix) { +char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model, + int mux_size, char* postfix) { char* mux_subckt_name = NULL; /* If the tgate spice model of this MUX is a MUX2 standard cell, @@ -2928,15 +2927,26 @@ char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, assert ( SPICE_MODEL_GATE_MUX2 == spice_model->design_tech_info.gate_info->type); mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name); } else { - mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 - + strlen(my_itoa(mux_size)) + strlen(postfix) + 1)); - sprintf(mux_subckt_name, "%s_size%d%s", - spice_model->name, mux_size, postfix); + mux_subckt_name = generate_verilog_mux_subckt_name(spice_model, mux_size, postfix); } return mux_subckt_name; } + +/* Generate the subckt name for a MUX module/submodule */ +char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, + int mux_size, char* postfix) { + char* mux_subckt_name = NULL; + + mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 + + strlen(my_itoa(mux_size)) + strlen(postfix) + 1)); + sprintf(mux_subckt_name, "%s_size%d%s", + spice_model->name, mux_size, postfix); + + return mux_subckt_name; +} + enum e_dump_verilog_port_type convert_spice_model_port_type_to_verilog_port_type(enum e_spice_model_port_type spice_model_port_type) { enum e_dump_verilog_port_type verilog_port_type; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index a66fd48f2..47b780804 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -221,6 +221,9 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model, t_spice_model* mem_model, char* postfix); +char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model, + int mux_size, char* postfix); + char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, int mux_size, char* postfix); From 32e3a556b9e12ff97318f2e22754adf495777ad3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jul 2019 09:26:05 -0600 Subject: [PATCH 06/21] bug fixing herited from explicit mapping --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index aa4525e9a..eb736e27e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -3213,7 +3213,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); - fprintf(fp, "is_explicit_mappingf\n"); + fprintf(fp, "`endif\n"); /* Call the MUX SPICE model */ From f10bce826aec6343845d32da1e069866879f830e Mon Sep 17 00:00:00 2001 From: egiacomin Date: Wed, 17 Jul 2019 12:07:40 -0600 Subject: [PATCH 07/21] Update README.md --- README.md | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/README.md b/README.md index 8d8b479fc..0e0d91c0d 100644 --- a/README.md +++ b/README.md @@ -1,35 +1,30 @@ # Getting Started with OpenFPGA - [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) ## Introduction - The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification testbenches/scripts. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.
## Compilation - Dependencies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md). -**Compilation steps:** -1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go into it* -2. mkdir build && cd build # *Create a folder named build in OpenPFGA repository* -3. cmake .. -DCMAKE_BUILD_TYPE=debug # *Create Makefile in this folder using cmake* +**Compilation Steps:** +1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go inside it* +2. mkdir build && cd build # *Create a folder named build in the OpenPFGA repository* +3. cmake .. -DCMAKE_BUILD_TYPE=debug # *Create a Makefile in this folder using cmake* 4. make # *Compile the tool and its dependencies* *We currently implemented OpenFPGA for:*
*1. Ubuntu 16.04*
*2. Red Hat 7.5*
*3. MacOS Mojave 10.13.4*

-*Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.* +*Please note that those were the versions for which the tool was tested. It might work with earlier versions and other distributions.* ## Documentation OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options. -## Tutorial - -You can find in the folder [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/tutorials). This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them. - -Through this tutorial users can learn how to use the flow and set the dependancies.
-The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md) will guide you through trainings and explain folder oraganization as well as referencing tips and used keywords. +## Tutorials +You can find some tutorials in the [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/tutorials) folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations. +Through those tutorials, users can learn how to use the flow and install the different dependencies.
+The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md) will guide you through training and explain the folder oraganization as well as introducing some tips and commonly used keywords. From 95b56f31d7e8a0a7263b07f632f58a44fda8c3ce Mon Sep 17 00:00:00 2001 From: egiacomin Date: Wed, 17 Jul 2019 12:11:38 -0600 Subject: [PATCH 08/21] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 0e0d91c0d..6d2f25e13 100644 --- a/README.md +++ b/README.md @@ -17,7 +17,7 @@ Dependencies and help using docker can be found at [**./tutorials/building.md**] *We currently implemented OpenFPGA for:*
*1. Ubuntu 16.04*
*2. Red Hat 7.5*
-*3. MacOS Mojave 10.13.4*

+*3. MacOS Mojave 10.14.4*

*Please note that those were the versions for which the tool was tested. It might work with earlier versions and other distributions.* ## Documentation From 1da04b9c3a960805fe134e2726fe5a9bdcf31699 Mon Sep 17 00:00:00 2001 From: egiacomin Date: Wed, 17 Jul 2019 12:19:57 -0600 Subject: [PATCH 09/21] Update tutorial_index.md --- tutorials/tutorial_index.md | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/tutorials/tutorial_index.md b/tutorials/tutorial_index.md index 8198fb6da..bbf95ff86 100644 --- a/tutorials/tutorial_index.md +++ b/tutorials/tutorial_index.md @@ -1,26 +1,20 @@ -# Tutorial introduction - -OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.
-Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.

-These tutorials are organized as follow: -* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md) +# Tutorial Introduction +OpenFPGA is an IP Verilog Generator allowing reliable and fast testing of homogeneous FPGA architectures.
+Its main goal is to easily and efficiently generated a complete customizable FPGA and uses a semi-custom design flow.

+In order to help you get in touch with the software, we provide few tutorials which are organized as follow: +* [Building the tool and his dependencies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md) * [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md) * Architecture modification -## Folder organization - +## Folder Organization OpenFPGA repository is organized as follow: * **abc**: open source synthesys tool * **ace2**: abc extension generating .act files +* **ace2**: abc extension generating activity files (.act) * **vpr7_x2p**: sources of modified vpr * **yosys**: opensource synthesys tool * **fpga_flow**: scripts and dependencies to run the complete flow -## Tips and informations - -Some keywords will be used during this tutorial: +## Tips and Information +Some keywords will be used during in the tutorials: * OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path - - - - From 922e40131fbf41638fe370da45ce751c69d92bc1 Mon Sep 17 00:00:00 2001 From: egiacomin Date: Wed, 17 Jul 2019 12:33:15 -0600 Subject: [PATCH 10/21] Update how2use.md --- tutorials/fpga_flow/how2use.md | 58 +++++++++++++++------------------- 1 file changed, 25 insertions(+), 33 deletions(-) diff --git a/tutorials/fpga_flow/how2use.md b/tutorials/fpga_flow/how2use.md index 0bbe343a0..905adb5d1 100644 --- a/tutorials/fpga_flow/how2use.md +++ b/tutorials/fpga_flow/how2use.md @@ -1,36 +1,31 @@ -# FPGA flow - -This tutorial will help the user to understand how to use OpenFPGA flow.
-During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/folder_organization.md). +# FPGA Flow +This tutorial will help the user to understand how to use the OpenFPGA flow.
+During this tutorial, we consider that the user starts in the OpenFPGA folder and we will use tips and information provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/folder_organization.md). ## Running fpga_flow.pl - A script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh. ### Experiment - cd fpga_flow
./tuto_fpga_flow.sh
### Explanation +The *fpga_flow.pl* script takes an architecture description file (.xml), generates its netlists and generates a bitstream to implement a benchmark on the FPGA fabric and verifis its correct implementation.
+When you open the perl script, you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allows us to make this tutorial generic by generating full path to the dependencies.
+The second one is **fpga_flow.pl**. This script launches the OpenFPGA flow and can be used with many different [options](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/options.md).
+There are 3 important things to observe here: +- All the FPGA-Verilog options have been activated +- fpga_flow.pl calls a configuration file through the "config_file" variable +- fpga_flow.pl calls a list of benchmark to be implemented and tested through the "bench_txt" variable -By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.
-When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.
-The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/options.md).
-There is 3 important things to see: -- All FPGA-Verilog options have been activated -- fpga_flow.pl calls a configuration file through "config_file" variable -- fpga_flow.pl calls a list of benchmark to implement and test through "bench_txt" variable - -### Configuration file - -In this file paths have to be full path. Relative path could lead to errors.
+### Configuration File +In this file, paths have to be defined as **absolute** paths as relative paths could lead to errors.
The file is organized in 3 parts: -* **dir_path**: provides all the tools and repository path -* **flow_conf**: provides information on how the flow run -* **csv_tags**: *to complete* +* **dir_path**: provides all the tool and repository paths +* **flow_conf**: provides information on how the flow runs +* **csv_tags**: *to be completed* -While empty the file is as follow: +When empty, the file is as follow: [dir_path]
script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts
@@ -64,33 +59,30 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St *This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf* -### Benchmark list - +### Benchmark List The benchmark folder contains 3 sub-folders: * **Blif**: contains .blif and .act of benchmarks * **List**: contains all benchmark list files * **Verilog**: contains Verilog designs -Blif and Verilog folders are organized by folders with the name of projects. **Folder, top module and top module file must share the same name.**
-The benchmark list file can contain as many benchmarks as available in the same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:
+Blif and Verilog folders are organized by folders using the name of the projects. **The folder, top module and top module file must share the same name.**
+The benchmark list file can contain as many benchmarks as available in the same folder targetted by the "benchmark_dir" variable from the configuration file. It's written as:
top_module/*.v,; where is the number of channel/wire between each block. *This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt* -## Modifying flow -Once dependancies are understood, we can modify the flow by changing the architecture and the route channel width. +## Modifying the Flow +Once the dependencies are understood, the flow can be modified by changing the architecture file and the route channel width. ### Experiment - * cd OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial -* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto.conf +* replace the architecture "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto.conf * cd OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List * replace "200" with "300" in tuto_benchmark.txt * cd OPENFPGAPATHKEYWORD/fpga_flow -* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto_fpga_flow.sh +* replace the architecture "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto_fpga_flow.sh * ./tuto_fpga_flow.sh -### Explanation - -With this last experiment we replace the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut6.pdf) with a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut8.pdf), which means a 8-inputs fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs). This architecture provides more modes for the CLB and the crossbar changed from a half-connected to a fully connected, implying bigger multiplexor between the CLB and LUT inputs. These requirement in term of interconnection will lead to the increase in routing channel width. Indeed, if the routing channel is to low, it could be impossible to route a benchmark or the FPGA output can be delayed. +### Explanations +With this last experiment, the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut6.pdf) was replaced by a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut8.pdf), which means that an 8-input fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs) is used. This architecture provides more modes for the CLB and the crossbar which is changed from a half-connected to a fully connected, implying bigger multiplexors between the CLB and LUT inputs. These requirements in term of interconnection will lead an increase in the routing channel width. Indeed, if the routing channel is too low, it could be impossible to route a benchmark or the FPGA output could be delayed. From e7b40f06b0266cca5e9f08897d0ea6a5ecae5eb1 Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 15:21:07 -0400 Subject: [PATCH 11/21] Add documentation for fracturable LUTs --- .../arch_lang/circuit_model_examples.rst | 42 +++++++++++++++---- 1 file changed, 35 insertions(+), 7 deletions(-) diff --git a/docs/source/arch_lang/circuit_model_examples.rst b/docs/source/arch_lang/circuit_model_examples.rst index 4063d2b4e..dd86441e1 100644 --- a/docs/source/arch_lang/circuit_model_examples.rst +++ b/docs/source/arch_lang/circuit_model_examples.rst @@ -215,6 +215,24 @@ SRAMs .. note:: The support SRAM modules should have a BL and a WL when the memory-bank-style configuration circuit is declared. Note that the WL should be the write/read enable signal, while BL is the data input. +Logic gates +----- + +.. code-block:: xml + + + + + + + + + +.. note:: The circuit model in the type of gate aims to support direct mapping to standard cells or customized cells provided by technology vendors or users. + +.. note:: The logic functionality of a gate can be defined through the XML keyword topology. Currently, OpenFPGA supports AND, OR and MUX2 gates. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported. + +.. note:: It may happen that the port sequence in generated Verilog netlists has conflicts with the port sequence in standard and customized cells. To avoid this, users can set the XML keyword dump_explicit_port_map to be true, which enables explicit port mapping are dumped. Users can specify the pin/port name in the standard cell library using the XML keyword lib_name. Multiplexers ------------ @@ -319,14 +337,16 @@ Look-Up Tables .. code-block:: xml - - + + + + - - - + + + .. note:: The SPICE netlists of LUT can be auto-generated or customized. @@ -335,7 +355,13 @@ Look-Up Tables Additional design parameters for LUTs: -* **lut_input_buffer:** Specify the buffer for the inputs of a LUT (gates of the internal multiplexer). +* **lut_input_buffer:** Define transistor-level description for the buffer for the inputs of a LUT (gates of the internal multiplexer). Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit. + +* **lut_input_inverter:** Define transistor-level description for the inverter for the inputs of a LUT (gates of the internal multiplexer). Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit. + + +* **lut_intermediate_buffer:** Define transistor-level description for the buffer locating at intermediate stages of internal multiplexer of a LUT. Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit. To customize the location, users can define an integer array in the XML keyword location_map. For example, "-1-1-" indicates buffer inseration to every two stages of the LUT multiplexer tree, considering a 6-input LUT. + Instructions of defining design parameters: @@ -343,7 +369,9 @@ Instructions of defining design parameters: * **pass_gate_logic:** Specify the pass-gates of the internal multiplexer, the same as the multiplexers. -* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist. +* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist. To support customizable LUTs, each type of port contain special keywords. For input ports, the keyword tri_state_map aims to customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, tri_state_map="----11" indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. The circuit_model_name of input port is used to specify which logic gates will be used to tri-state the inputs in fracturable LUT modes. It is required to use an AND gate to force logic '0' or an OR gate to force logic '1' for the input ports. For output ports, the keyword lut_frac_level is used to specify the level in LUT multiplexer tree where the output port are wired to. For example, lut_frac_level="4" in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. The keyword lut_output_mask describes which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. lut_output_mask="0,2" indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. Note that the size of the output port should be consistent to the length of lut_output_mask. + +* **SRAM port for mode selection:** To enable switch between different operating modes, the SRAM bits of a fracturable LUT consists of two parts: configuration memory and mode selecting. The SRAM port for mode selection is specified through the XML keyword mode_select. Note that the size of such SRAM port should be consistent to the number of 1s or 0s in the tri_state_map. **LUT example** From 5bec11bd6ebc30b6c9ef13348a39f0c0b64b3705 Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 17:46:25 -0400 Subject: [PATCH 12/21] try to add logo --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 6d2f25e13..b7ca50c2c 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,5 @@ # Getting Started with OpenFPGA +![OpenFPGA](./docs/source/figures/OpenFPGA_logo.png) [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) From 6af0d277a2d0a7817784712cbc6801269ef6a961 Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 17:48:01 -0400 Subject: [PATCH 13/21] hot fix on fpga logo --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index b7ca50c2c..321b0d05d 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # Getting Started with OpenFPGA -![OpenFPGA](./docs/source/figures/OpenFPGA_logo.png) +![OpenFPGA](https://github.com/LNIS-Projects/OpenFPGA/blob/dev/docs/source/figures/OpenFPGA_logo.png) [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) From 17308621bdbc1a8cfc7ee2e6da61f0e85a99b1bc Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 17:53:36 -0400 Subject: [PATCH 14/21] resize logo on README --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index b7ca50c2c..2b2e50559 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # Getting Started with OpenFPGA -![OpenFPGA](./docs/source/figures/OpenFPGA_logo.png) +![OpenFPGA](./docs/source/figures/OpenFPGA_logo.png =100x) [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) From b850610cea485b453c0d3f7943fe3fca18c4e7b3 Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 17:55:10 -0400 Subject: [PATCH 15/21] resize logo to fit --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 2b2e50559..d8d3957d7 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # Getting Started with OpenFPGA -![OpenFPGA](./docs/source/figures/OpenFPGA_logo.png =100x) + [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) From b104de02635624abe7c4b05159bdf82ba5da46fe Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 17:56:06 -0400 Subject: [PATCH 16/21] resize logo again --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index d8d3957d7..94c50fb95 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ + # Getting Started with OpenFPGA - [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) From f3ed949c4b8663e7146bf7cf3229edec87292472 Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 18:36:49 -0400 Subject: [PATCH 17/21] retry placing images --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 94c50fb95..6d9e0a856 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,5 @@ + # Getting Started with OpenFPGA [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) From 37abd8af40408a8bd01dc27e6382bccfccf4c947 Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 18:40:26 -0400 Subject: [PATCH 18/21] try to place inline logo --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 6d9e0a856..3a9e39fff 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ - + -# Getting Started with OpenFPGA +# ![Getting Started with OpenFPGA](./docs/source/figures/OpenFPGA_logo.png) [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) From a80199057d4b929fe39b493980c8959e8b692ee6 Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 18:43:17 -0400 Subject: [PATCH 19/21] logo placement --- README.md | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/README.md b/README.md index 3a9e39fff..4be51ab3a 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,4 @@ - - -# ![Getting Started with OpenFPGA](./docs/source/figures/OpenFPGA_logo.png) +# Getting Started with OpenFPGA [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) From 8226f42d3d86b538f7743d16577113d8f1cb54eb Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 18:46:14 -0400 Subject: [PATCH 20/21] use hfill to place image inline --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 4be51ab3a..d4c6a99d4 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# Getting Started with OpenFPGA +# Getting Started with OpenFPGA [][hfill] [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) From 173440ffc3e9984d0eb758107b978e1f98cfc3e7 Mon Sep 17 00:00:00 2001 From: Xifan Tang Date: Wed, 17 Jul 2019 18:46:54 -0400 Subject: [PATCH 21/21] retry --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index d4c6a99d4..f8b1888ea 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# Getting Started with OpenFPGA [][hfill] +# Getting Started with OpenFPGA [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)