diff --git a/openfpga/test_blif/and.act b/openfpga/test_blif/and.act deleted file mode 100644 index 0f77bc6b3..000000000 --- a/openfpga/test_blif/and.act +++ /dev/null @@ -1,3 +0,0 @@ -a 0.5 0.5 -b 0.5 0.5 -c 0.25 0.25 diff --git a/openfpga/test_blif/and.blif b/openfpga/test_blif/and.blif deleted file mode 100644 index 67d978741..000000000 --- a/openfpga/test_blif/and.blif +++ /dev/null @@ -1,8 +0,0 @@ -.model top -.inputs a b -.outputs c - -.names a b c -11 1 - -.end diff --git a/openfpga/test_blif/and.v b/openfpga/test_blif/and.v deleted file mode 100644 index 876f1c6fe..000000000 --- a/openfpga/test_blif/and.v +++ /dev/null @@ -1,14 +0,0 @@ -`timescale 1ns / 1ps - -module top( - a, - b, - c); - -input wire a; -input wire b; -output wire c; - -assign c = a & b; - -endmodule diff --git a/openfpga/test_blif/and_latch.act b/openfpga/test_blif/and_latch.act deleted file mode 100644 index 61bbe1fe8..000000000 --- a/openfpga/test_blif/and_latch.act +++ /dev/null @@ -1,6 +0,0 @@ -a 0.492800 0.201000 -b 0.502000 0.197200 -clk 0.500000 2.000000 -d 0.240200 0.171200 -c 0.240200 0.044100 -n1 0.240200 0.044100 diff --git a/openfpga/test_blif/and_latch.blif b/openfpga/test_blif/and_latch.blif deleted file mode 100644 index dbd863d9c..000000000 --- a/openfpga/test_blif/and_latch.blif +++ /dev/null @@ -1,14 +0,0 @@ -# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020 -.model top -.inputs a b clk -.outputs c d - -.latch n1 d re clk 0 - -.names a b c -11 1 - -.names c n1 -1 1 - -.end diff --git a/openfpga/test_blif/and_latch.v b/openfpga/test_blif/and_latch.v deleted file mode 100644 index 893cdf7a4..000000000 --- a/openfpga/test_blif/and_latch.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns / 1ps - -module top( - clk, - a, - b, - c, - d); - -input wire clk; - -input wire a; -input wire b; -output wire c; -output reg d; - -assign c = a & b; - -always @(posedge clk) begin - d <= c; -end - -endmodule diff --git a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml deleted file mode 100644 index de0602e1e..000000000 --- a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml +++ /dev/null @@ -1,228 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml deleted file mode 100644 index 51e250a8a..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ /dev/null @@ -1,260 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml deleted file mode 100644 index ae08c8250..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ /dev/null @@ -1,285 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml deleted file mode 100644 index cb145e06d..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ /dev/null @@ -1,302 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml deleted file mode 100644 index e65851291..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ /dev/null @@ -1,314 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml deleted file mode 100644 index 65117d199..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ /dev/null @@ -1,285 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml deleted file mode 100644 index 779880dea..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ /dev/null @@ -1,288 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml deleted file mode 100644 index 621847439..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ /dev/null @@ -1,294 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml deleted file mode 100644 index 159214507..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ /dev/null @@ -1,264 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml deleted file mode 100644 index 59f493a13..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ /dev/null @@ -1,252 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml deleted file mode 100644 index d04318510..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ /dev/null @@ -1,251 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga deleted file mode 100644 index 90f20b2b7..000000000 --- a/openfpga/test_script/and_k6_frac.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges --verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -write_fabric_hierarchy --file ./fabric_hierarchy.txt - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/and.bitstream - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --hierarchical --file /var/tmp/xtang/openfpga_test_src/SDC_hie -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga deleted file mode 100644 index 3cdebb2b1..000000000 --- a/openfpga/test_script/and_k6_frac_adder_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga deleted file mode 100644 index 34ec11181..000000000 --- a/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable.openfpga b/openfpga/test_script/and_k6_frac_tileable.openfpga deleted file mode 100644 index 0731e6543..000000000 --- a/openfpga/test_script/and_k6_frac_tileable.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga deleted file mode 100644 index 05ea64bce..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga +++ /dev/null @@ -1,64 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist - write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC \ - --explicit_port_mapping --include_timing --include_signal_init \ - --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga deleted file mode 100644 index ed0d8cc5a..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga deleted file mode 100644 index 492c70ea6..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga deleted file mode 100644 index 29830f1db..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga deleted file mode 100644 index 22a658a73..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga deleted file mode 100644 index 466c3bcd0..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga deleted file mode 100644 index fbcdda185..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga deleted file mode 100644 index 864fea78d..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga +++ /dev/null @@ -1,63 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc \ - --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga b/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga deleted file mode 100644 index 7b9fa407c..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga b/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga deleted file mode 100644 index 04ff99d8c..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga deleted file mode 100644 index 5b1177586..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga b/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga deleted file mode 100644 index 95cd2a3c3..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac.openfpga b/openfpga/test_script/and_latch_k6_frac.openfpga deleted file mode 100644 index b41ac4450..000000000 --- a/openfpga/test_script/and_latch_k6_frac.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and_latch' design -vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack --verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable.openfpga deleted file mode 100644 index c89174d2d..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and_latch' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack --verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga deleted file mode 100644 index ef49426d0..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga deleted file mode 100644 index 87c69c880..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_vpr_arch/k6_N10_40nm.xml b/openfpga/test_vpr_arch/k6_N10_40nm.xml deleted file mode 100644 index 83b4948a8..000000000 --- a/openfpga/test_vpr_arch/k6_N10_40nm.xml +++ /dev/null @@ -1,299 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml deleted file mode 100644 index ceacbb3f2..000000000 --- a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml +++ /dev/null @@ -1,299 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml deleted file mode 100644 index 8476a5155..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml +++ /dev/null @@ -1,441 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml deleted file mode 100644 index 1fb82be72..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml +++ /dev/null @@ -1,644 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml deleted file mode 100644 index e0d7ce812..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml deleted file mode 100644 index 146a170e5..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml +++ /dev/null @@ -1,441 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml deleted file mode 100644 index 8f1dfd10e..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml +++ /dev/null @@ -1,644 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml deleted file mode 100644 index 8254a0583..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml deleted file mode 100644 index 35eedb327..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml +++ /dev/null @@ -1,805 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - aib.tx_clk aib.tx_data aib.rx_clk aib.rx_data - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml deleted file mode 100644 index d23c34960..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml +++ /dev/null @@ -1,773 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io_top.outpad io_top.inpad - - - - - - - - - - - io_right.outpad io_right.inpad - - - - - - - - - - - io_bottom.outpad io_bottom.inpad - - - - - - - - - - - io_left.outpad io_left.inpad - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml deleted file mode 100644 index bb06c5f39..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml +++ /dev/null @@ -1,742 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml deleted file mode 100644 index 1bb8ffe23..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml deleted file mode 100644 index 77dedbcb0..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml +++ /dev/null @@ -1,696 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin clb.regin - clb.O[9:0] clb.I[19:0] - clb.cout clb.regout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - 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clb.cout clb.regout clb.scout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -